sourcemod-central: sourcepawn/vm/jit/x86/jit_x86.cpp@55682fa202ea (annotated)

dvander@68	1	#include <string.h>
dvander@68	2	#include <stdlib.h>
dvander@68	3	#include "jit_x86.h"
dvander@70	4	#include "opcode_helpers.h"
dvander@70	5	#include "x86_macros.h"
dvander@68	6
dvander@70	7	inline void WriteOp_Move_Pri(JitWriter *jit)
dvander@69	8	{
dvander@70	9	//mov eax, edx
dvander@70	10	IA32_Mov_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@70	11	}
dvander@69	12
dvander@70	13	inline void WriteOp_Move_Alt(JitWriter *jit)
dvander@70	14	{
dvander@70	15	//mov edx, eax
dvander@70	16	IA32_Mov_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_PRI, MOD_REG);
dvander@70	17	}
dvander@70	18
dvander@70	19	inline void WriteOp_Xchg(JitWriter *jit)
dvander@70	20	{
dvander@71	21	/* :TODO: change this? XCHG is bad */
dvander@70	22	//xchg eax, edx
dvander@70	23	IA32_Xchg_Eax_Reg(jit, AMX_REG_ALT);
dvander@70	24	}
dvander@69	25
dvander@70	26	inline void WriteOp_Push(JitWriter *jit)
dvander@70	27	{
dvander@70	28	//push stack, DAT offset based
dvander@70	29	//sub ebp, 4
dvander@70	30	//mov ecx, [edi+<val>]
dvander@70	31	//mov [ebp], ecx
dvander@70	32	cell_t val = jit->read_cell();
dvander@70	33	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@70	34	//optimize encoding a bit...
dvander@70	35	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@70	36	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_DAT, (jit_int8_t)val);
dvander@70	37	else
dvander@70	38	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_DAT, val);
dvander@70	39	IA32_Mov_Rm_Reg(jit, AMX_REG_STK, AMX_REG_TMP, MOD_MEM_REG);
dvander@70	40	}
dvander@69	41
dvander@71	42	inline void WriteOp_Push_C(JitWriter *jit)
dvander@71	43	{
dvander@71	44	//push stack
dvander@71	45	//mov [ebp-4], <val>
dvander@71	46	//sub ebp, 4
dvander@71	47	cell_t val = jit->read_cell();
dvander@71	48	IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_STK, val, -4);
dvander@71	49	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	50	}
dvander@71	51
dvander@71	52	inline void WriteOp_Zero(JitWriter *jit)
dvander@71	53	{
dvander@71	54	//mov [edi+<val>], 0
dvander@71	55	cell_t val = jit->read_cell();
dvander@71	56	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	57	IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_DAT, 0, (jit_int8_t)val);
dvander@71	58	else
dvander@71	59	IA32_Mov_Rm_Imm32_Disp32(jit, AMX_REG_DAT, 0, val);
dvander@71	60	}
dvander@71	61
dvander@71	62	inline void WriteOp_Zero_S(JitWriter *jit)
dvander@71	63	{
dvander@71	64	//mov [ebx+<val>], 0
dvander@71	65	cell_t val = jit->read_cell();
dvander@71	66	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	67	IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_FRM, 0, (jit_int8_t)val);
dvander@71	68	else
dvander@71	69	IA32_Mov_Rm_Imm32_Disp32(jit, AMX_REG_FRM, 0, val);
dvander@71	70	}
dvander@71	71
dvander@70	72	inline void WriteOp_Push_S(JitWriter *jit)
dvander@70	73	{
dvander@70	74	//push stack, FRM offset based
dvander@70	75	//sub ebp, 4
dvander@70	76	//mov ecx, [ebx+<val>]
dvander@70	77	//mov [ebp], ecx
dvander@70	78	cell_t val = jit->read_cell();
dvander@70	79	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@70	80	//optimize encoding a bit...
dvander@70	81	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@70	82	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_FRM, (jit_int8_t)val);
dvander@70	83	else
dvander@70	84	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_FRM, val);
dvander@70	85	IA32_Mov_Rm_Reg(jit, AMX_REG_STK, AMX_REG_TMP, MOD_MEM_REG);
dvander@70	86	}
dvander@69	87
dvander@71	88	inline void WriteOp_Push_Pri(JitWriter *jit)
dvander@71	89	{
dvander@71	90	//mov [ebp-4], eax
dvander@71	91	//sub ebp, 4
dvander@71	92	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_PRI, -4);
dvander@71	93	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	94	}
dvander@71	95
dvander@71	96	inline void WriteOp_Push_Alt(JitWriter *jit)
dvander@71	97	{
dvander@71	98	//mov [ebp-4], edx
dvander@71	99	//sub ebp, 4
dvander@71	100	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_ALT, -4);
dvander@71	101	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	102	}
dvander@71	103
dvander@71	104	inline void WriteOp_Push2_C(JitWriter *jit)
dvander@71	105	{
dvander@71	106	Macro_PushN_C(jit, 2);
dvander@71	107	}
dvander@71	108
dvander@71	109	inline void WriteOp_Push3_C(JitWriter *jit)
dvander@71	110	{
dvander@71	111	Macro_PushN_C(jit, 3);
dvander@71	112	}
dvander@71	113
dvander@70	114	inline void WriteOp_Push4_C(JitWriter *jit)
dvander@70	115	{
dvander@70	116	Macro_PushN_C(jit, 4);
dvander@70	117	}
dvander@69	118
dvander@70	119	inline void WriteOp_Push5_C(JitWriter *jit)
dvander@70	120	{
dvander@70	121	Macro_PushN_C(jit, 5);
dvander@70	122	}
dvander@70	123
dvander@70	124	inline void WriteOp_Push2_Adr(JitWriter *jit)
dvander@70	125	{
dvander@70	126	Macro_PushN_Addr(jit, 2);
dvander@70	127	}
dvander@70	128
dvander@70	129	inline void WriteOp_Push3_Adr(JitWriter *jit)
dvander@70	130	{
dvander@70	131	Macro_PushN_Addr(jit, 3);
dvander@70	132	}
dvander@70	133
dvander@70	134	inline void WriteOp_Push4_Adr(JitWriter *jit)
dvander@70	135	{
dvander@70	136	Macro_PushN_Addr(jit, 4);
dvander@70	137	}
dvander@70	138
dvander@70	139	inline void WriteOp_Push5_Adr(JitWriter *jit)
dvander@70	140	{
dvander@70	141	Macro_PushN_Addr(jit, 5);
dvander@70	142	}
dvander@70	143
dvander@70	144	inline void WriteOp_Push2_S(JitWriter *jit)
dvander@70	145	{
dvander@70	146	Macro_PushN_S(jit, 2);
dvander@70	147	}
dvander@69	148
dvander@70	149	inline void WriteOp_Push3_S(JitWriter *jit)
dvander@70	150	{
dvander@70	151	Macro_PushN_S(jit, 3);
dvander@70	152	}
dvander@70	153
dvander@70	154	inline void WriteOp_Push4_S(JitWriter *jit)
dvander@70	155	{
dvander@70	156	Macro_PushN_S(jit, 4);
dvander@70	157	}
dvander@70	158
dvander@70	159	inline void WriteOp_Push5_S(JitWriter *jit)
dvander@70	160	{
dvander@70	161	Macro_PushN_S(jit, 5);
dvander@70	162	}
dvander@69	163
dvander@70	164	inline void WriteOp_Push5(JitWriter *jit)
dvander@70	165	{
dvander@70	166	Macro_PushN(jit, 5);
dvander@70	167	}
dvander@69	168
dvander@70	169	inline void WriteOp_Push4(JitWriter *jit)
dvander@70	170	{
dvander@70	171	Macro_PushN(jit, 4);
dvander@70	172	}
dvander@70	173
dvander@70	174	inline void WriteOp_Push3(JitWriter *jit)
dvander@70	175	{
dvander@70	176	Macro_PushN(jit, 3);
dvander@70	177	}
dvander@70	178
dvander@70	179	inline void WriteOp_Push2(JitWriter *jit)
dvander@70	180	{
dvander@70	181	Macro_PushN(jit, 2);
dvander@69	182	}
dvander@69	183
dvander@71	184	inline void WriteOp_Zero_Pri(JitWriter *jit)
dvander@71	185	{
dvander@71	186	//xor eax, eax
dvander@71	187	IA32_Xor_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_PRI, MOD_REG);
dvander@71	188	}
dvander@71	189
dvander@71	190	inline void WriteOp_Zero_Alt(JitWriter *jit)
dvander@71	191	{
dvander@71	192	//xor edx, edx
dvander@71	193	IA32_Xor_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_ALT, MOD_REG);
dvander@71	194	}
dvander@71	195
dvander@71	196	inline void WriteOp_Add(JitWriter *jit)
dvander@71	197	{
dvander@71	198	//add eax, edx
dvander@71	199	IA32_Add_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	200	}
dvander@71	201
dvander@71	202	inline void WriteOp_Sub(JitWriter *jit)
dvander@71	203	{
dvander@71	204	//sub eax, edx
dvander@71	205	IA32_Sub_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	206	}
dvander@71	207
dvander@71	208	inline void WriteOp_Sub_Alt(JitWriter *jit)
dvander@71	209	{
dvander@71	210	//neg eax
dvander@71	211	//add eax, edx
dvander@71	212	IA32_Neg_Rm(jit, AMX_REG_PRI, MOD_REG);
dvander@71	213	IA32_Add_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	214	}
dvander@71	215
dvander@71	216	inline void WriteOp_Proc(JitWriter *jit)
dvander@71	217	{
dvander@71	218	//push old frame on stack:
dvander@71	219	//sub ebp, 4
dvander@73	220	//mov ecx, [frm]
dvander@71	221	//mov [ebp], ecx
dvander@71	222	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	223	IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_INFO_FRM, MOD_MEM_REG);
dvander@71	224	IA32_Mov_Rm_Reg(jit, AMX_REG_STK, AMX_REG_TMP, MOD_MEM_REG);
dvander@71	225	//save frame:
dvander@73	226	//mov [frm], ebp - get new frame
dvander@73	227	//mov ebx, ebp - store frame back
dvander@73	228	//sub [frm], edi - relocate local frame
dvander@73	229	IA32_Mov_Rm_Reg(jit, AMX_INFO_FRM, AMX_REG_STK, MOD_MEM_REG);
dvander@71	230	IA32_Mov_Rm_Reg(jit, AMX_REG_FRM, AMX_REG_STK, MOD_REG);
dvander@71	231	IA32_Sub_Rm_Reg(jit, AMX_INFO_FRM, AMX_REG_DAT, MOD_MEM_REG);
dvander@71	232	}
dvander@71	233
dvander@71	234	inline void WriteOp_Shl(JitWriter *jit)
dvander@71	235	{
dvander@71	236	//mov ecx, edx
dvander@71	237	//shl eax, cl
dvander@71	238	IA32_Mov_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
dvander@71	239	IA32_Shl_Rm_CL(jit, AMX_REG_PRI, MOD_REG);
dvander@71	240	}
dvander@71	241
dvander@71	242	inline void WriteOp_Shr(JitWriter *jit)
dvander@71	243	{
dvander@71	244	//mov ecx, edx
dvander@71	245	//shr eax, cl
dvander@71	246	IA32_Mov_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
dvander@71	247	IA32_Shr_Rm_CL(jit, AMX_REG_PRI, MOD_REG);
dvander@71	248	}
dvander@71	249
dvander@71	250	inline void WriteOp_Sshr(JitWriter *jit)
dvander@71	251	{
dvander@71	252	//mov ecx, edx
dvander@71	253	//sar eax, cl
dvander@71	254	IA32_Mov_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
dvander@71	255	IA32_Sar_Rm_CL(jit, AMX_REG_PRI, MOD_REG);
dvander@71	256	}
dvander@71	257
dvander@71	258	inline void WriteOp_Shl_C_Pri(JitWriter *jit)
dvander@71	259	{
dvander@71	260	//shl eax, <val>
dvander@71	261	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
dvander@71	262	IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
dvander@71	263	}
dvander@71	264
dvander@71	265	inline void WriteOp_Shl_C_Alt(JitWriter *jit)
dvander@71	266	{
dvander@71	267	//shl edx, <val>
dvander@71	268	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
dvander@71	269	IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
dvander@71	270	}
dvander@71	271
dvander@71	272	inline void WriteOp_Shr_C_Pri(JitWriter *jit)
dvander@71	273	{
dvander@71	274	//shr eax, <val>
dvander@71	275	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
dvander@71	276	IA32_Shr_Rm_Imm8(jit, AMX_REG_PRI, val, MOD_REG);
dvander@71	277	}
dvander@71	278
dvander@71	279	inline void WriteOp_Shr_C_Alt(JitWriter *jit)
dvander@71	280	{
dvander@71	281	//shr edx, <val>
dvander@71	282	jit_uint8_t val = (jit_uint8_t)jit->read_cell();
dvander@71	283	IA32_Shr_Rm_Imm8(jit, AMX_REG_ALT, val, MOD_REG);
dvander@71	284	}
dvander@71	285
dvander@71	286	inline void WriteOp_SMul(JitWriter *jit)
dvander@71	287	{
dvander@71	288	//mov ecx, edx
dvander@71	289	//imul edx
dvander@71	290	//mov edx, ecx
dvander@71	291	IA32_Mov_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
dvander@71	292	IA32_IMul_Rm(jit, AMX_REG_ALT, MOD_REG);
dvander@71	293	IA32_Mov_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_TMP, MOD_REG);
dvander@71	294	}
dvander@71	295
dvander@71	296	inline void WriteOp_UMul(JitWriter *jit)
dvander@71	297	{
dvander@71	298	//mov ecx, edx
dvander@71	299	//mul edx
dvander@71	300	//mov edx, ecx
dvander@71	301	IA32_Mov_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_ALT, MOD_REG);
dvander@71	302	IA32_Mul_Rm(jit, AMX_REG_ALT, MOD_REG);
dvander@71	303	IA32_Mov_Rm_Reg(jit, AMX_REG_ALT, AMX_REG_TMP, MOD_REG);
dvander@71	304	}
dvander@71	305
dvander@71	306	inline void WriteOp_Not(JitWriter *jit)
dvander@71	307	{
dvander@71	308	//test eax, eax
dvander@71	309	//mov eax, 0
dvander@71	310	//sete al
dvander@71	311	IA32_Test_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_PRI, MOD_REG);
dvander@71	312	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	313	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_E);
dvander@71	314	}
dvander@71	315
dvander@71	316	inline void WriteOp_Neg(JitWriter *jit)
dvander@71	317	{
dvander@71	318	//neg eax
dvander@71	319	IA32_Neg_Rm(jit, AMX_REG_PRI, MOD_REG);
dvander@71	320	}
dvander@71	321
dvander@71	322	inline void WriteOp_Xor(JitWriter *jit)
dvander@71	323	{
dvander@71	324	//xor eax, edx
dvander@71	325	IA32_Xor_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	326	}
dvander@71	327
dvander@71	328	inline void WriteOp_Or(JitWriter *jit)
dvander@71	329	{
dvander@71	330	//or eax, edx
dvander@71	331	IA32_Or_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	332	}
dvander@71	333
dvander@71	334	inline void WriteOp_And(JitWriter *jit)
dvander@71	335	{
dvander@71	336	//and eax, edx
dvander@71	337	IA32_And_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	338	}
dvander@71	339
dvander@71	340	inline void WriteOp_Invert(JitWriter *jit)
dvander@71	341	{
dvander@71	342	//not eax
dvander@71	343	IA32_Not_Rm(jit, AMX_REG_PRI, MOD_REG);
dvander@71	344	}
dvander@71	345
dvander@71	346	inline void WriteOp_Add_C(JitWriter *jit)
dvander@71	347	{
dvander@71	348	//add eax, <val>
dvander@71	349	cell_t val = jit->read_cell();
dvander@71	350	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	351	IA32_Add_Rm_Imm8(jit, AMX_REG_PRI, (jit_int8_t)val, MOD_REG);
dvander@71	352	else
dvander@71	353	IA32_Add_Eax_Imm32(jit, val);
dvander@71	354	}
dvander@71	355
dvander@71	356	inline void WriteOp_SMul_C(JitWriter *jit)
dvander@71	357	{
dvander@71	358	//imul eax, <val>
dvander@71	359	cell_t val = jit->read_cell();
dvander@71	360	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	361	IA32_IMul_Reg_Imm8(jit, AMX_REG_PRI, MOD_REG, (jit_int8_t)val);
dvander@71	362	else
dvander@71	363	IA32_IMul_Reg_Imm32(jit, AMX_REG_PRI, MOD_REG, val);
dvander@71	364	}
dvander@71	365
dvander@71	366	inline void WriteOp_Sign_Pri(JitWriter *jit)
dvander@71	367	{
dvander@71	368	//shl eax, 24
dvander@71	369	//sar eax, 24
dvander@71	370	IA32_Shl_Rm_Imm8(jit, AMX_REG_PRI, 24, MOD_REG);
dvander@71	371	IA32_Sar_Rm_Imm8(jit, AMX_REG_PRI, 24, MOD_REG);
dvander@71	372	}
dvander@71	373
dvander@71	374	inline void WriteOp_Sign_Alt(JitWriter *jit)
dvander@71	375	{
dvander@71	376	//shl edx, 24
dvander@71	377	//sar edx, 24
dvander@71	378	IA32_Shl_Rm_Imm8(jit, AMX_REG_ALT, 24, MOD_REG);
dvander@71	379	IA32_Sar_Rm_Imm8(jit, AMX_REG_ALT, 24, MOD_REG);
dvander@71	380	}
dvander@71	381
dvander@71	382	inline void WriteOp_Eq(JitWriter *jit)
dvander@71	383	{
dvander@71	384	//cmp eax, edx ; PRI == ALT ?
dvander@71	385	//mov eax, 0
dvander@71	386	//sete al
dvander@71	387	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	388	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	389	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_E);
dvander@71	390	}
dvander@71	391
dvander@71	392	inline void WriteOp_Neq(JitWriter *jit)
dvander@71	393	{
dvander@71	394	//cmp eax, edx ; PRI != ALT ?
dvander@71	395	//mov eax, 0
dvander@71	396	//setne al
dvander@71	397	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	398	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	399	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_NE);
dvander@71	400	}
dvander@71	401
dvander@71	402	inline void WriteOp_Less(JitWriter *jit)
dvander@71	403	{
dvander@71	404	//cmp eax, edx ; PRI < ALT ? (unsigned)
dvander@71	405	//mov eax, 0
dvander@71	406	//setb al
dvander@71	407	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	408	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	409	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_B);
dvander@71	410	}
dvander@71	411
dvander@71	412	inline void WriteOp_Leq(JitWriter *jit)
dvander@71	413	{
dvander@71	414	//cmp eax, edx ; PRI <= ALT ? (unsigned)
dvander@71	415	//mov eax, 0
dvander@71	416	//setbe al
dvander@71	417	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	418	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	419	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_BE);
dvander@71	420	}
dvander@71	421
dvander@71	422	inline void WriteOp_Grtr(JitWriter *jit)
dvander@71	423	{
dvander@71	424	//cmp eax, edx ; PRI > ALT ? (unsigned)
dvander@71	425	//mov eax, 0
dvander@71	426	//seta al
dvander@71	427	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	428	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	429	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_A);
dvander@71	430	}
dvander@71	431
dvander@71	432	inline void WriteOp_Geq(JitWriter *jit)
dvander@71	433	{
dvander@71	434	//cmp eax, edx ; PRI >= ALT ? (unsigned)
dvander@71	435	//mov eax, 0
dvander@71	436	//setae al
dvander@71	437	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	438	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	439	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_AE);
dvander@71	440	}
dvander@71	441
dvander@71	442	inline void WriteOp_Sless(JitWriter *jit)
dvander@71	443	{
dvander@71	444	//cmp eax, edx ; PRI < ALT ? (signed)
dvander@71	445	//mov eax, 0
dvander@71	446	//setl al
dvander@71	447	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	448	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	449	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_L);
dvander@71	450	}
dvander@71	451
dvander@71	452	inline void WriteOp_Sleq(JitWriter *jit)
dvander@71	453	{
dvander@71	454	//cmp eax, edx ; PRI <= ALT ? (signed)
dvander@71	455	//mov eax, 0
dvander@71	456	//setle al
dvander@71	457	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	458	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	459	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_LE);
dvander@71	460	}
dvander@71	461
dvander@71	462	inline void WriteOp_Sgrtr(JitWriter *jit)
dvander@71	463	{
dvander@71	464	//cmp eax, edx ; PRI > ALT ? (signed)
dvander@71	465	//mov eax, 0
dvander@71	466	//setg al
dvander@71	467	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	468	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	469	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_G);
dvander@71	470	}
dvander@71	471
dvander@71	472	inline void WriteOp_Sgeq(JitWriter *jit)
dvander@71	473	{
dvander@71	474	//cmp eax, edx ; PRI >= ALT ? (signed)
dvander@71	475	//mov eax, 0
dvander@71	476	//setge al
dvander@71	477	IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_ALT, MOD_REG);
dvander@71	478	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	479	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_GE);
dvander@71	480	}
dvander@71	481
dvander@71	482	inline void WriteOp_Eq_C_Pri(JitWriter *jit)
dvander@71	483	{
dvander@71	484	//cmp eax, <val> ; PRI == value ?
dvander@71	485	//mov eax, 0
dvander@71	486	//sete al
dvander@71	487	cell_t val = jit->read_cell();
dvander@71	488	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	489	IA32_Cmp_Rm_Imm8(jit, MOD_REG, AMX_REG_PRI, (jit_int8_t)val);
dvander@71	490	else
dvander@71	491	IA32_Cmp_Eax_Imm32(jit, val);
dvander@71	492	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, 0);
dvander@71	493	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_E);
dvander@71	494	}
dvander@71	495
dvander@71	496	inline void WriteOp_Eq_C_Alt(JitWriter *jit)
dvander@71	497	{
dvander@71	498	//xor eax, eax
dvander@71	499	//cmp edx, <val> ; ALT == value ?
dvander@71	500	//sete al
dvander@71	501	cell_t val = jit->read_cell();
dvander@71	502	IA32_Xor_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_PRI, MOD_REG);
dvander@71	503	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	504	IA32_Cmp_Rm_Imm8(jit, MOD_REG, AMX_REG_ALT, (jit_int8_t)val);
dvander@71	505	else
dvander@71	506	IA32_Cmp_Rm_Imm32(jit, MOD_REG, AMX_REG_ALT, val);
dvander@71	507	IA32_SetCC_Rm8(jit, AMX_REG_PRI, CC_E);
dvander@71	508	}
dvander@71	509
dvander@71	510	inline void WriteOp_Inc_Pri(JitWriter *jit)
dvander@71	511	{
dvander@71	512	//add eax, 1
dvander@71	513	IA32_Add_Rm_Imm8(jit, AMX_REG_PRI, 1, MOD_REG);
dvander@71	514	}
dvander@71	515
dvander@71	516	inline void WriteOp_Inc_Alt(JitWriter *jit)
dvander@71	517	{
dvander@71	518	//add edx, 1
dvander@71	519	IA32_Add_Rm_Imm8(jit, AMX_REG_ALT, 1, MOD_REG);
dvander@71	520	}
dvander@71	521
dvander@71	522	inline void WriteOp_Inc(JitWriter *jit)
dvander@71	523	{
dvander@71	524	//add [edi+<val>], 1
dvander@71	525	cell_t val = jit->read_cell();
dvander@71	526	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	527	IA32_Add_Rm_Imm8_Disp8(jit, AMX_REG_DAT, 1, (jit_int8_t)val);
dvander@71	528	else
dvander@71	529	IA32_Add_Rm_Imm8_Disp32(jit, AMX_REG_DAT, 1, val);
dvander@71	530	}
dvander@71	531
dvander@71	532	inline void WriteOp_Inc_S(JitWriter *jit)
dvander@71	533	{
dvander@71	534	//add [ebx+<val>], 1
dvander@71	535	cell_t val = jit->read_cell();
dvander@71	536	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	537	IA32_Add_Rm_Imm8_Disp8(jit, AMX_REG_FRM, 1, (jit_int8_t)val);
dvander@71	538	else
dvander@71	539	IA32_Add_Rm_Imm8_Disp32(jit, AMX_REG_FRM, 1, val);
dvander@71	540	}
dvander@71	541
dvander@71	542	inline void WriteOp_Inc_I(JitWriter *jit)
dvander@71	543	{
dvander@71	544	//add [edi+eax], 1
dvander@71	545	IA32_Add_Rm_Imm8_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_PRI, NOSCALE, 1);
dvander@71	546	}
dvander@71	547
dvander@71	548	inline void WriteOp_Dec_Pri(JitWriter *jit)
dvander@71	549	{
dvander@71	550	//sub eax, 1
dvander@71	551	IA32_Sub_Rm_Imm8(jit, AMX_REG_PRI, 1, MOD_REG);
dvander@71	552	}
dvander@71	553
dvander@71	554	inline void WriteOp_Dec_Alt(JitWriter *jit)
dvander@71	555	{
dvander@71	556	//sub edx, 1
dvander@71	557	IA32_Sub_Rm_Imm8(jit, AMX_REG_ALT, 1, MOD_REG);
dvander@71	558	}
dvander@71	559
dvander@71	560	inline void WriteOp_Dec(JitWriter *jit)
dvander@71	561	{
dvander@71	562	//sub [edi+<val>], 1
dvander@71	563	cell_t val = jit->read_cell();
dvander@71	564	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	565	IA32_Sub_Rm_Imm8_Disp8(jit, AMX_REG_DAT, 1, (jit_int8_t)val);
dvander@71	566	else
dvander@71	567	IA32_Sub_Rm_Imm8_Disp32(jit, AMX_REG_DAT, 1, val);
dvander@71	568	}
dvander@71	569
dvander@71	570	inline void WriteOp_Dec_S(JitWriter *jit)
dvander@71	571	{
dvander@71	572	//sub [ebx+<val>], 1
dvander@71	573	cell_t val = jit->read_cell();
dvander@71	574	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	575	IA32_Sub_Rm_Imm8_Disp8(jit, AMX_REG_FRM, 1, (jit_int8_t)val);
dvander@71	576	else
dvander@71	577	IA32_Sub_Rm_Imm8_Disp32(jit, AMX_REG_FRM, 1, val);
dvander@71	578	}
dvander@71	579
dvander@71	580	inline void WriteOp_Dec_I(JitWriter *jit)
dvander@71	581	{
dvander@71	582	//sub [edi+eax], 1
dvander@71	583	IA32_Sub_Rm_Imm8_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_PRI, NOSCALE, 1);
dvander@71	584	}
dvander@71	585
dvander@71	586	inline void WriteOp_Load_Pri(JitWriter *jit)
dvander@71	587	{
dvander@71	588	//mov eax, [edi+<val>]
dvander@71	589	cell_t val = jit->read_cell();
dvander@71	590	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	591	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	592	else
dvander@71	593	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_PRI, AMX_REG_DAT, val);
dvander@71	594	}
dvander@71	595
dvander@71	596	inline void WriteOp_Load_Alt(JitWriter *jit)
dvander@71	597	{
dvander@71	598	//mov edx, [edi+<val>]
dvander@71	599	cell_t val = jit->read_cell();
dvander@71	600	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	601	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	602	else
dvander@71	603	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_ALT, AMX_REG_DAT, val);
dvander@71	604	}
dvander@71	605
dvander@71	606	inline void WriteOp_Load_S_Pri(JitWriter *jit)
dvander@71	607	{
dvander@71	608	//mov eax, [ebx+<val>]
dvander@71	609	cell_t val = jit->read_cell();
dvander@71	610	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	611	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	612	else
dvander@71	613	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_PRI, AMX_REG_FRM, val);
dvander@71	614	}
dvander@71	615
dvander@71	616	inline void WriteOp_Load_S_Alt(JitWriter *jit)
dvander@71	617	{
dvander@71	618	//mov edx, [ebx+<val>]
dvander@71	619	cell_t val = jit->read_cell();
dvander@71	620	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	621	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	622	else
dvander@71	623	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_ALT, AMX_REG_FRM, val);
dvander@71	624	}
dvander@71	625
dvander@71	626	inline void WriteOp_Lref_Pri(JitWriter *jit)
dvander@71	627	{
dvander@71	628	//mov eax, [edi+<val>]
dvander@71	629	//mov eax, [edi+eax]
dvander@71	630	cell_t val = jit->read_cell();
dvander@71	631	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	632	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	633	else
dvander@71	634	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_PRI, AMX_REG_DAT, val);
dvander@71	635	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_PRI, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
dvander@71	636	}
dvander@71	637
dvander@71	638	inline void WriteOp_Lref_Alt(JitWriter *jit)
dvander@71	639	{
dvander@71	640	//mov edx, [edi+<val>]
dvander@71	641	//mov edx, [edi+edx]
dvander@71	642	cell_t val = jit->read_cell();
dvander@71	643	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	644	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	645	else
dvander@71	646	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_ALT, AMX_REG_DAT, val);
dvander@71	647	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_ALT, AMX_REG_DAT, AMX_REG_ALT, NOSCALE);
dvander@71	648	}
dvander@71	649
dvander@71	650	inline void WriteOp_Lref_S_Pri(JitWriter *jit)
dvander@71	651	{
dvander@71	652	//mov eax, [ebx+<val>]
dvander@71	653	//mov eax, [edi+eax]
dvander@71	654	cell_t val = jit->read_cell();
dvander@71	655	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	656	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	657	else
dvander@71	658	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_PRI, AMX_REG_FRM, val);
dvander@71	659	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_PRI, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
dvander@71	660	}
dvander@71	661
dvander@71	662	inline void WriteOp_Lref_S_Alt(JitWriter *jit)
dvander@71	663	{
dvander@71	664	//mov edx, [ebx+<val>]
dvander@71	665	//mov edx, [edi+edx]
dvander@71	666	cell_t val = jit->read_cell();
dvander@71	667	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	668	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	669	else
dvander@71	670	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_ALT, AMX_REG_FRM, val);
dvander@71	671	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_ALT, AMX_REG_DAT, AMX_REG_ALT, NOSCALE);
dvander@71	672	}
dvander@71	673
dvander@71	674	inline void WriteOp_Const_Pri(JitWriter *jit)
dvander@71	675	{
dvander@71	676	//mov eax, <val>
dvander@71	677	cell_t val = jit->read_cell();
dvander@71	678	IA32_Mov_Reg_Imm32(jit, AMX_REG_PRI, val);
dvander@71	679	}
dvander@71	680
dvander@71	681	inline void WriteOp_Const_Alt(JitWriter *jit)
dvander@71	682	{
dvander@71	683	//mov edx, <val>
dvander@71	684	cell_t val = jit->read_cell();
dvander@71	685	IA32_Mov_Reg_Imm32(jit, AMX_REG_ALT, val);
dvander@71	686	}
dvander@71	687
dvander@71	688	inline void WriteOp_Addr_Pri(JitWriter *jit)
dvander@71	689	{
dvander@71	690	//mov eax, frm
dvander@71	691	//add eax, <val>
dvander@71	692	cell_t val = jit->read_cell();
dvander@71	693	IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_INFO_FRM, MOD_MEM_REG);
dvander@71	694	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	695	IA32_Add_Rm_Imm8(jit, AMX_REG_PRI, (jit_int8_t)val, MOD_REG);
dvander@71	696	else
dvander@71	697	IA32_Add_Eax_Imm32(jit, val);
dvander@71	698	}
dvander@71	699
dvander@71	700	inline void WriteOp_Addr_Alt(JitWriter *jit)
dvander@71	701	{
dvander@71	702	//mov edx, frm
dvander@71	703	//add edx, <val>
dvander@71	704	cell_t val = jit->read_cell();
dvander@71	705	IA32_Mov_Reg_Rm(jit, AMX_REG_ALT, AMX_INFO_FRM, MOD_MEM_REG);
dvander@71	706	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	707	IA32_Add_Rm_Imm8(jit, AMX_REG_ALT, (jit_int8_t)val, MOD_REG);
dvander@71	708	else
dvander@71	709	IA32_Add_Rm_Imm32(jit, AMX_REG_ALT, val, MOD_REG);
dvander@71	710	}
dvander@71	711
dvander@71	712	inline void WriteOp_Stor_Pri(JitWriter *jit)
dvander@71	713	{
dvander@71	714	//mov [edi+<val>], eax
dvander@71	715	cell_t val = jit->read_cell();
dvander@71	716	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	717	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_DAT, AMX_REG_PRI, (jit_int8_t)val);
dvander@71	718	else
dvander@71	719	IA32_Mov_Rm_Reg_Disp32(jit, AMX_REG_DAT, AMX_REG_PRI, val);
dvander@71	720	}
dvander@71	721
dvander@71	722	inline void WriteOp_Stor_Alt(JitWriter *jit)
dvander@71	723	{
dvander@71	724	//mov [edi+<val>], edx
dvander@71	725	cell_t val = jit->read_cell();
dvander@71	726	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	727	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_DAT, AMX_REG_ALT, (jit_int8_t)val);
dvander@71	728	else
dvander@71	729	IA32_Mov_Rm_Reg_Disp32(jit, AMX_REG_DAT, AMX_REG_ALT, val);
dvander@71	730	}
dvander@71	731
dvander@71	732	inline void WriteOp_Stor_S_Pri(JitWriter *jit)
dvander@71	733	{
dvander@71	734	//mov [ebx+<val>], eax
dvander@71	735	cell_t val = jit->read_cell();
dvander@71	736	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	737	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_FRM, AMX_REG_PRI, (jit_int8_t)val);
dvander@71	738	else
dvander@71	739	IA32_Mov_Rm_Reg_Disp32(jit, AMX_REG_FRM, AMX_REG_PRI, val);
dvander@71	740	}
dvander@71	741
dvander@71	742	inline void WriteOp_Stor_S_Alt(JitWriter *jit)
dvander@71	743	{
dvander@71	744	//mov [ebx+<val>], edx
dvander@71	745	cell_t val = jit->read_cell();
dvander@71	746	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	747	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_FRM, AMX_REG_ALT, (jit_int8_t)val);
dvander@71	748	else
dvander@71	749	IA32_Mov_Rm_Reg_Disp32(jit, AMX_REG_FRM, AMX_REG_ALT, val);
dvander@71	750	}
dvander@71	751
dvander@71	752	inline void WriteOp_Idxaddr(JitWriter *jit)
dvander@71	753	{
dvander@71	754	//lea eax, [edx+4*eax]
dvander@71	755	IA32_Lea_Reg_DispRegMult(jit, AMX_REG_PRI, AMX_REG_ALT, AMX_REG_PRI, SCALE4);
dvander@71	756	}
dvander@71	757
dvander@71	758	inline void WriteOp_Sref_Pri(JitWriter *jit)
dvander@71	759	{
dvander@71	760	//mov ecx, [edi+<val>]
dvander@71	761	//mov [edi+ecx], eax
dvander@71	762	cell_t val = jit->read_cell();
dvander@71	763	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	764	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	765	else
dvander@71	766	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_DAT, val);
dvander@71	767	IA32_Mov_Rm_Reg_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, AMX_REG_PRI);
dvander@71	768	}
dvander@71	769
dvander@71	770	inline void WriteOp_Sref_Alt(JitWriter *jit)
dvander@71	771	{
dvander@71	772	//mov ecx, [edi+<val>]
dvander@71	773	//mov [edi+ecx], edx
dvander@71	774	cell_t val = jit->read_cell();
dvander@71	775	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	776	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_DAT, (jit_int8_t)val);
dvander@71	777	else
dvander@71	778	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_DAT, val);
dvander@71	779	IA32_Mov_Rm_Reg_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, AMX_REG_ALT);
dvander@71	780	}
dvander@71	781
dvander@71	782	inline void WriteOp_Sref_S_Pri(JitWriter *jit)
dvander@71	783	{
dvander@71	784	//mov ecx, [ebx+<val>]
dvander@71	785	//mov [edi+ecx], eax
dvander@71	786	cell_t val = jit->read_cell();
dvander@71	787	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	788	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	789	else
dvander@71	790	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_FRM, val);
dvander@71	791	IA32_Mov_Rm_Reg_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, AMX_REG_PRI);
dvander@71	792	}
dvander@71	793
dvander@71	794	inline void WriteOp_Sref_S_Alt(JitWriter *jit)
dvander@71	795	{
dvander@71	796	//mov ecx, [ebx+<val>]
dvander@71	797	//mov [edi+ecx], edx
dvander@71	798	cell_t val = jit->read_cell();
dvander@71	799	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	800	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_FRM, (jit_int8_t)val);
dvander@71	801	else
dvander@71	802	IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_FRM, val);
dvander@71	803	IA32_Mov_Rm_Reg_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, AMX_REG_ALT);
dvander@71	804	}
dvander@71	805
dvander@71	806	inline void WriteOp_Align_Pri(JitWriter *jit)
dvander@71	807	{
dvander@71	808	//xor eax, <cellsize - val>
dvander@71	809	cell_t val = sizeof(cell_t) - jit->read_cell();
dvander@71	810	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	811	IA32_Xor_Rm_Imm8(jit, AMX_REG_PRI, MOD_REG, (jit_int8_t)val);
dvander@71	812	else
dvander@71	813	IA32_Xor_Eax_Imm32(jit, val);
dvander@71	814	}
dvander@71	815
dvander@71	816	inline void WriteOp_Align_Alt(JitWriter *jit)
dvander@71	817	{
dvander@71	818	//xor edx, <cellsize - val>
dvander@71	819	cell_t val = sizeof(cell_t) - jit->read_cell();
dvander@71	820	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	821	IA32_Xor_Rm_Imm8(jit, AMX_REG_ALT, MOD_REG, (jit_int8_t)val);
dvander@71	822	else
dvander@71	823	IA32_Xor_Rm_Imm32(jit, AMX_REG_ALT, MOD_REG, val);
dvander@71	824	}
dvander@71	825
dvander@71	826	inline void WriteOp_Pop_Pri(JitWriter *jit)
dvander@71	827	{
dvander@71	828	//mov eax, [ebp]
dvander@71	829	//add ebp, 4
dvander@71	830	IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_REG_STK, MOD_MEM_REG);
dvander@71	831	IA32_Add_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	832	}
dvander@71	833
dvander@71	834	inline void WriteOp_Pop_Alt(JitWriter *jit)
dvander@71	835	{
dvander@71	836	//mov edx, [ebp]
dvander@71	837	//add ebp, 4
dvander@71	838	IA32_Mov_Reg_Rm(jit, AMX_REG_ALT, AMX_REG_STK, MOD_MEM_REG);
dvander@71	839	IA32_Add_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	840	}
dvander@71	841
dvander@71	842	inline void WriteOp_Swap_Pri(JitWriter *jit)
dvander@71	843	{
dvander@71	844	//xchg [ebp], eax // :TODO: change this xchg for another thing (SLOW!! :O )
dvander@71	845	IA32_Xchg_Rm_Reg(jit, AMX_REG_STK, AMX_REG_PRI, MOD_MEM_REG);
dvander@71	846	}
dvander@71	847
dvander@71	848	inline void WriteOp_Swap_Alt(JitWriter *jit)
dvander@71	849	{
dvander@71	850	//xchg [ebp], edx // :TODO: change this xchg for another thing
dvander@71	851	IA32_Xchg_Rm_Reg(jit, AMX_REG_STK, AMX_REG_ALT, MOD_MEM_REG);
dvander@71	852	}
dvander@71	853
dvander@71	854	inline void WriteOp_PushAddr(JitWriter *jit)
dvander@71	855	{
dvander@71	856	//mov ecx, frm ;get address (offset from frame)
dvander@71	857	//add ecx, <val>
dvander@71	858	//mov [ebp-4], ecx
dvander@71	859	//sub ebp, 4
dvander@71	860	cell_t val = jit->read_cell();
dvander@71	861	IA32_Mov_Reg_Rm(jit, AMX_REG_TMP, AMX_INFO_FRM, MOD_MEM_REG);
dvander@71	862	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	863	IA32_Add_Rm_Imm8(jit, AMX_REG_TMP, (jit_int8_t)val, MOD_REG);
dvander@71	864	else
dvander@71	865	IA32_Add_Rm_Imm32(jit, AMX_REG_TMP, val, MOD_REG);
dvander@71	866	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_TMP, -4);
dvander@71	867	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4, MOD_REG);
dvander@71	868	}
dvander@71	869
dvander@71	870	inline void WriteOp_Movs(JitWriter *jit)
dvander@71	871	{
dvander@71	872	//cld
dvander@71	873	//push esi
dvander@71	874	//lea esi, [edi+eax]
dvander@71	875	//add edi, edx
dvander@71	876	//if dword:
dvander@71	877	// mov ecx, dword
dvander@71	878	// rep movsd
dvander@71	879	//if byte:
dvander@71	880	// mov ecx, byte
dvander@71	881	// rep movsb
dvander@71	882	//sub edi, edx
dvander@71	883	//sub edi, <val>
dvander@71	884	//pop esi
dvander@71	885	cell_t val = jit->read_cell();
dvander@71	886	unsigned int dwords = val >> 2;
dvander@71	887	unsigned int bytes = val & 0x3;
dvander@71	888
dvander@71	889	IA32_Cld(jit);
dvander@71	890	IA32_Push_Reg(jit, REG_ESI);
dvander@71	891	IA32_Lea_Reg_DispRegMult(jit, REG_ESI, REG_EDI, AMX_REG_PRI, NOSCALE);
dvander@71	892	IA32_Add_Rm_Reg(jit, REG_EDI, AMX_REG_ALT, MOD_REG);
dvander@71	893	if (dwords)
dvander@71	894	{
dvander@71	895	IA32_Mov_Reg_Imm32(jit, AMX_REG_TMP, dwords);
dvander@71	896	IA32_Rep(jit);
dvander@71	897	IA32_Movsd(jit);
dvander@71	898	}
dvander@71	899	if (bytes)
dvander@71	900	{
dvander@71	901	IA32_Mov_Reg_Imm32(jit, AMX_REG_TMP, bytes);
dvander@71	902	IA32_Rep(jit);
dvander@71	903	IA32_Movsb(jit);
dvander@71	904	}
dvander@71	905	IA32_Sub_Rm_Reg(jit, REG_EDI, AMX_REG_ALT, MOD_REG);
dvander@71	906	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	907	IA32_Sub_Rm_Imm8(jit, REG_EDI, (jit_uint8_t)val, MOD_REG);
dvander@71	908	else
dvander@71	909	IA32_Sub_Rm_Imm32(jit, REG_EDI, val, MOD_REG);
dvander@71	910	IA32_Pop_Reg(jit, REG_ESI);
dvander@71	911	}
dvander@71	912
dvander@71	913	inline void WriteOp_Fill(JitWriter *jit)
dvander@71	914	{
dvander@71	915	//add edi, edx
dvander@71	916	//mov ecx, <val> >> 2
dvander@71	917	//cld
dvander@71	918	//rep stosd
dvander@71	919	//sub edi, edx
dvander@71	920	//sub edi, <val> >> 2
dvander@71	921	unsigned int val = jit->read_cell() >> 2;
dvander@71	922
dvander@71	923	IA32_Add_Rm_Reg(jit, REG_EDI, AMX_REG_ALT, MOD_REG);
dvander@71	924	IA32_Mov_Reg_Imm32(jit, AMX_REG_TMP, val);
dvander@71	925	IA32_Cld(jit);
dvander@71	926	IA32_Rep(jit);
dvander@71	927	IA32_Stosd(jit);
dvander@71	928	IA32_Sub_Rm_Reg(jit, REG_EDI, AMX_REG_ALT, MOD_REG);
dvander@71	929	if (val < SCHAR_MAX && val > SCHAR_MIN)
dvander@71	930	IA32_Sub_Rm_Imm8(jit, REG_EDI, (jit_uint8_t)val, MOD_REG);
dvander@71	931	else
dvander@71	932	IA32_Sub_Rm_Imm32(jit, REG_EDI, val, MOD_REG);
dvander@71	933	}
dvander@71	934
dvander@71	935	inline void WriteOp_Heap_Pri(JitWriter *jit)
dvander@71	936	{
dvander@73	937	//mov edx, [hea]
dvander@73	938	//add [hea], eax
dvander@73	939	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, AMX_REG_INFO, AMX_INFO_HEAP);
dvander@73	940	IA32_Add_Rm_Reg_Disp8(jit, AMX_REG_INFO, AMX_REG_PRI, AMX_INFO_HEAP);
dvander@71	941	}
dvander@71	942
dvander@71	943	inline void WriteOp_Push_Heap_C(JitWriter *jit)
dvander@71	944	{
dvander@73	945	//mov ecx, [hea]
dvander@71	946	//mov [edi+ecx], <val>
dvander@73	947	//add [hea], 4
dvander@71	948	cell_t val = jit->read_cell();
dvander@73	949	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAP);
dvander@71	950	IA32_Mov_Rm_Imm32_Disp_Reg(jit, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, val);
dvander@73	951	IA32_Add_Rm_Imm8_Disp8(jit, AMX_REG_INFO, 4, AMX_INFO_HEAP);
dvander@71	952	}
dvander@71	953
dvander@71	954	inline void WriteOp_Pop_Heap_Pri(JitWriter *jit)
dvander@71	955	{
dvander@73	956	//sub [hea], 4
dvander@71	957	//mov ecx, [hea]
dvander@71	958	//mov eax, [edi+ecx]
dvander@73	959	IA32_Sub_Rm_Imm8_Disp8(jit, AMX_REG_INFO, 4, AMX_INFO_HEAP);
dvander@73	960	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAP);
dvander@71	961	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_PRI, AMX_REG_DAT, AMX_REG_TMP, NOSCALE);
dvander@71	962	}
dvander@71	963
dvander@72	964	inline void WriteOp_Load_Both(JitWriter *jit)
dvander@72	965	{
dvander@72	966	WriteOp_Const_Pri(jit);
dvander@72	967	WriteOp_Const_Alt(jit);
dvander@72	968	}
dvander@72	969
dvander@72	970	inline void WriteOp_Load_S_Both(JitWriter *jit)
dvander@72	971	{
dvander@72	972	WriteOp_Load_S_Pri(jit);
dvander@72	973	WriteOp_Load_S_Alt(jit);
dvander@72	974	}
dvander@72	975
dvander@72	976	inline void WriteOp_Const(JitWriter *jit)
dvander@72	977	{
dvander@72	978	//mov [edi+<addr>], <val>
dvander@72	979	cell_t addr = jit->read_cell();
dvander@72	980	cell_t val = jit->read_cell();
dvander@72	981	if (addr < SCHAR_MAX && addr > SCHAR_MIN)
dvander@72	982	{
dvander@72	983	IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_DAT, val, (jit_int8_t)addr);
dvander@72	984	} else {
dvander@72	985	IA32_Mov_Rm_Imm32_Disp32(jit, AMX_REG_DAT, val, addr);
dvander@72	986	}
dvander@72	987	}
dvander@72	988
dvander@72	989	inline void WriteOp_Const_S(JitWriter *jit)
dvander@72	990	{
dvander@72	991	//mov [ebx+<offs>], <val>
dvander@72	992	cell_t offs = jit->read_cell();
dvander@72	993	cell_t val = jit->read_cell();
dvander@72	994
dvander@72	995	if (offs < SCHAR_MAX && offs > SCHAR_MIN)
dvander@72	996	{
dvander@72	997	IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_FRM, val, (jit_int8_t)offs);
dvander@72	998	} else {
dvander@72	999	IA32_Mov_Rm_Imm32_Disp32(jit, AMX_REG_FRM, val, offs);
dvander@72	1000	}
dvander@72	1001	}
dvander@72	1002
dvander@75	1003	inline void WriteOp_Load_I(JitWriter *jit)
dvander@75	1004	{
dvander@75	1005	//mov eax, [edi+eax]
dvander@75	1006	Write_Check_VerifyAddr(jit, REG_EAX, false);
dvander@75	1007	IA32_Mov_Reg_Rm_Disp_Reg(jit, AMX_REG_PRI, AMX_REG_DAT, AMX_REG_PRI, NOSCALE);
dvander@75	1008	}
dvander@75	1009
dvander@72	1010
dvander@71	1011	/*************************************************
dvander@71	1012	*************************************************
dvander@71	1013	* JIT PROPER ************************************
dvander@71	1014	* The rest of the from now on is the JIT engine *
dvander@71	1015	*************************************************
dvander@71	1016	*************************************************/
dvander@71	1017
dvander@71	1018
dvander@69	1019	IPluginContext JITX86::CompileToContext(ICompilation co, int *err)
dvander@69	1020	{
dvander@69	1021	CompData data = (CompData )co;
dvander@69	1022	sp_plugin_t *plugin = data->plugin;
dvander@69	1023
dvander@69	1024	/* The first phase is to browse */
dvander@69	1025	uint8_t *code = plugin->pcode;
dvander@69	1026	uint8_t *cip;
dvander@69	1027	uint8_t *end_cip = plugin->pcode + plugin->pcode_size;
dvander@69	1028	OPCODE op;
dvander@69	1029	int op_c;
dvander@69	1030	uint32_t reloc_count = 0;
dvander@69	1031
dvander@69	1032	/* FIRST PASS (light load) - Get initial opcode information */
dvander@69	1033	for (cip = code; cip < end_cip;)
dvander@69	1034	{
dvander@69	1035	op = (OPCODE)(ucell_t )cip;
dvander@69	1036	if ((unsigned)op >= OP_NUM_OPCODES)
dvander@69	1037	{
dvander@69	1038	AbortCompilation(co);
dvander@69	1039	*err = SP_ERR_INVALID_INSTRUCTION;
dvander@69	1040	return NULL;
dvander@69	1041	}
dvander@69	1042	cip += sizeof(cell_t);
dvander@69	1043	op_c = OpAdvTable[op];
dvander@69	1044	if (op_c >= 0)
dvander@69	1045	{
dvander@69	1046	cip += op_c;
dvander@69	1047	} else if (op_c == -3) {
dvander@69	1048	AbortCompilation(co);
dvander@69	1049	*err = SP_ERR_INVALID_INSTRUCTION;
dvander@69	1050	return NULL;
dvander@69	1051	} else if (op_c == -2) {
dvander@69	1052	reloc_count++;
dvander@69	1053	cip += sizeof(cell_t);
dvander@69	1054	} else if (op_c == -1) {
dvander@69	1055	switch (op)
dvander@69	1056	{
dvander@69	1057	case OP_CASETBL:
dvander@69	1058	{
dvander@69	1059	ucell_t num = (ucell_t )cip;
dvander@69	1060	cip += sizeof(cell_t);
dvander@69	1061	reloc_count += (num + 1);
dvander@69	1062	cip += ((2num) + 1) sizeof(cell_t);
dvander@69	1063	break;
dvander@69	1064	}
dvander@69	1065	default:
dvander@69	1066	{
dvander@69	1067	AbortCompilation(co);
dvander@69	1068	*err = SP_ERR_INVALID_INSTRUCTION;
dvander@69	1069	return NULL;
dvander@69	1070	}
dvander@69	1071	}
dvander@69	1072	}
dvander@69	1073	}
dvander@69	1074
dvander@71	1075	/*********************************************
dvander@71	1076	* SECOND PASS (medium load): writer.outbase is NULL, getting size only
dvander@71	1077	* THIRD PASS (heavy load!!): writer.outbase is valid and output is written
dvander@71	1078	*********************************************/
dvander@71	1079
dvander@70	1080	JitWriter writer;
dvander@74	1081	JitWriter *jit = &writer;
dvander@74	1082	cell_t endptr = (cell_t )(end_cip);
dvander@70	1083
dvander@74	1084	/* Initial code is written "blank,"
dvander@74	1085	* so we can check the exact memory usage.
dvander@74	1086	*/
dvander@70	1087	writer.inptr = (cell_t *)code;
dvander@70	1088	writer.outptr = NULL;
dvander@70	1089	writer.outbase = NULL;
dvander@70	1090
dvander@74	1091	/* Get inlining level */
dvander@74	1092	int inline_level = data->inline_level;
dvander@74	1093
dvander@74	1094	//:TODO: Jump back here once finished!
dvander@75	1095
dvander@74	1096	/* Start writing the actual code */
dvander@75	1097	data->jit_return = Write_Execute_Function(jit);
dvander@75	1098
dvander@75	1099	/* Write error checking routines in case they are needed */
dvander@75	1100	data->jit_verify_addr_eax = jit->jit_curpos();
dvander@75	1101	Write_Check_VerifyAddr(jit, REG_EAX, true);
dvander@75	1102	data->jit_verify_addr_edx = jit->jit_curpos();
dvander@75	1103	Write_Check_VerifyAddr(jit, REG_EDX, true);
dvander@74	1104
dvander@70	1105	for (; writer.inptr <= endptr;)
dvander@70	1106	{
dvander@70	1107	op = (OPCODE)writer.read_cell();
dvander@70	1108	switch (op)
dvander@70	1109	{
dvander@70	1110	case OP_MOVE_PRI:
dvander@70	1111	{
dvander@70	1112	WriteOp_Move_Pri(jit);
dvander@70	1113	break;
dvander@70	1114	}
dvander@70	1115	case OP_MOVE_ALT:
dvander@70	1116	{
dvander@70	1117	WriteOp_Move_Alt(jit);
dvander@70	1118	break;
dvander@70	1119	}
dvander@70	1120	case OP_XCHG:
dvander@70	1121	{
dvander@70	1122	WriteOp_Xchg(jit);
dvander@70	1123	break;
dvander@70	1124	}
dvander@70	1125	case OP_PUSH:
dvander@70	1126	{
dvander@70	1127	WriteOp_Push(jit);
dvander@70	1128	break;
dvander@70	1129	}
dvander@70	1130	case OP_PUSH_S:
dvander@70	1131	{
dvander@70	1132	WriteOp_Push_S(jit);
dvander@70	1133	break;
dvander@70	1134	}
dvander@71	1135	case OP_PUSH2_C:
dvander@71	1136	{
dvander@71	1137	WriteOp_Push2_C(jit);
dvander@71	1138	break;
dvander@71	1139	}
dvander@71	1140	case OP_PUSH3_C:
dvander@71	1141	{
dvander@71	1142	WriteOp_Push3(jit);
dvander@71	1143	break;
dvander@71	1144	}
dvander@70	1145	case OP_PUSH4_C:
dvander@70	1146	{
dvander@70	1147	WriteOp_Push4_C(jit);
dvander@70	1148	break;
dvander@70	1149	}
dvander@70	1150	case OP_PUSH5_C:
dvander@70	1151	{
dvander@70	1152	WriteOp_Push5_C(jit);
dvander@70	1153	break;
dvander@70	1154	}
dvander@70	1155	case OP_PUSH2_ADR:
dvander@70	1156	{
dvander@70	1157	WriteOp_Push2_Adr(jit);
dvander@70	1158	break;
dvander@70	1159	}
dvander@70	1160	case OP_PUSH3_ADR:
dvander@70	1161	{
dvander@70	1162	WriteOp_Push3_Adr(jit);
dvander@70	1163	break;
dvander@70	1164	}
dvander@70	1165	case OP_PUSH4_ADR:
dvander@70	1166	{
dvander@70	1167	WriteOp_Push4_Adr(jit);
dvander@70	1168	break;
dvander@70	1169	}
dvander@70	1170	case OP_PUSH5_ADR:
dvander@70	1171	{
dvander@70	1172	WriteOp_Push5_Adr(jit);
dvander@70	1173	break;
dvander@70	1174	}
dvander@70	1175	case OP_PUSH2_S:
dvander@70	1176	{
dvander@70	1177	WriteOp_Push2_S(jit);
dvander@70	1178	break;
dvander@70	1179	}
dvander@70	1180	case OP_PUSH3_S:
dvander@70	1181	{
dvander@70	1182	WriteOp_Push3_S(jit);
dvander@70	1183	break;
dvander@70	1184	}
dvander@70	1185	case OP_PUSH4_S:
dvander@70	1186	{
dvander@70	1187	WriteOp_Push4_S(jit);
dvander@70	1188	break;
dvander@70	1189	}
dvander@70	1190	case OP_PUSH5_S:
dvander@70	1191	{
dvander@70	1192	WriteOp_Push5_S(jit);
dvander@70	1193	break;
dvander@70	1194	}
dvander@70	1195	case OP_PUSH5:
dvander@70	1196	{
dvander@70	1197	WriteOp_Push5(jit);
dvander@70	1198	break;
dvander@70	1199	}
dvander@70	1200	case OP_PUSH4:
dvander@70	1201	{
dvander@70	1202	WriteOp_Push4(jit);
dvander@70	1203	break;
dvander@70	1204	}
dvander@70	1205	case OP_PUSH3:
dvander@70	1206	{
dvander@70	1207	WriteOp_Push3(jit);
dvander@70	1208	break;
dvander@70	1209	}
dvander@70	1210	case OP_PUSH2:
dvander@70	1211	{
dvander@70	1212	WriteOp_Push2(jit);
dvander@70	1213	break;
dvander@70	1214	}
dvander@71	1215	case OP_ZERO_PRI:
dvander@71	1216	{
dvander@71	1217	WriteOp_Zero_Pri(jit);
dvander@71	1218	break;
dvander@71	1219	}
dvander@71	1220	case OP_ZERO_ALT:
dvander@71	1221	{
dvander@71	1222	WriteOp_Zero_Alt(jit);
dvander@71	1223	break;
dvander@71	1224	}
dvander@71	1225	case OP_PROC:
dvander@71	1226	{
dvander@71	1227	WriteOp_Proc(jit);
dvander@71	1228	break;
dvander@71	1229	}
dvander@71	1230	case OP_SHL:
dvander@71	1231	{
dvander@71	1232	WriteOp_Shl(jit);
dvander@71	1233	break;
dvander@71	1234	}
dvander@71	1235	case OP_SHR:
dvander@71	1236	{
dvander@71	1237	WriteOp_Shr(jit);
dvander@71	1238	break;
dvander@71	1239	}
dvander@71	1240	case OP_SSHR:
dvander@71	1241	{
dvander@71	1242	WriteOp_Sshr(jit);
dvander@71	1243	break;
dvander@71	1244	}
dvander@71	1245	case OP_SHL_C_PRI:
dvander@71	1246	{
dvander@71	1247	WriteOp_Shl_C_Pri(jit);
dvander@71	1248	break;
dvander@71	1249	}
dvander@71	1250	case OP_SHL_C_ALT:
dvander@71	1251	{
dvander@71	1252	WriteOp_Shl_C_Alt(jit);
dvander@71	1253	break;
dvander@71	1254	}
dvander@71	1255	case OP_SHR_C_PRI:
dvander@71	1256	{
dvander@71	1257	WriteOp_Shr_C_Pri(jit);
dvander@71	1258	break;
dvander@71	1259	}
dvander@71	1260	case OP_SHR_C_ALT:
dvander@71	1261	{
dvander@71	1262	WriteOp_Shr_C_Alt(jit);
dvander@71	1263	break;
dvander@71	1264	}
dvander@71	1265	case OP_SMUL:
dvander@71	1266	{
dvander@71	1267	WriteOp_SMul(jit);
dvander@71	1268	break;
dvander@71	1269	}
dvander@71	1270	case OP_UMUL:
dvander@71	1271	{
dvander@71	1272	WriteOp_UMul(jit);
dvander@71	1273	break;
dvander@71	1274	}
dvander@71	1275	case OP_ADD:
dvander@71	1276	{
dvander@71	1277	WriteOp_Add(jit);
dvander@71	1278	break;
dvander@71	1279	}
dvander@71	1280	case OP_SUB:
dvander@71	1281	{
dvander@71	1282	WriteOp_Sub(jit);
dvander@71	1283	break;
dvander@71	1284	}
dvander@71	1285	case OP_SUB_ALT:
dvander@71	1286	{
dvander@71	1287	WriteOp_Sub_Alt(jit);
dvander@71	1288	break;
dvander@71	1289	}
dvander@71	1290	case OP_NOP:
dvander@71	1291	{
dvander@71	1292	/* do nothing */
dvander@71	1293	break;
dvander@71	1294	}
dvander@71	1295	case OP_NOT:
dvander@71	1296	{
dvander@71	1297	WriteOp_Not(jit);
dvander@71	1298	break;
dvander@71	1299	}
dvander@71	1300	case OP_NEG:
dvander@71	1301	{
dvander@71	1302	WriteOp_Neg(jit);
dvander@71	1303	break;
dvander@71	1304	}
dvander@71	1305	case OP_XOR:
dvander@71	1306	{
dvander@71	1307	WriteOp_Xor(jit);
dvander@71	1308	break;
dvander@71	1309	}
dvander@71	1310	case OP_OR:
dvander@71	1311	{
dvander@71	1312	WriteOp_Or(jit);
dvander@71	1313	break;
dvander@71	1314	}
dvander@71	1315	case OP_AND:
dvander@71	1316	{
dvander@71	1317	WriteOp_And(jit);
dvander@71	1318	break;
dvander@71	1319	}
dvander@71	1320	case OP_INVERT:
dvander@71	1321	{
dvander@71	1322	WriteOp_Invert(jit);
dvander@71	1323	break;
dvander@71	1324	}
dvander@71	1325	case OP_ADD_C:
dvander@71	1326	{
dvander@71	1327	WriteOp_Add_C(jit);
dvander@71	1328	break;
dvander@71	1329	}
dvander@71	1330	case OP_SMUL_C:
dvander@71	1331	{
dvander@71	1332	WriteOp_SMul_C(jit);
dvander@71	1333	break;
dvander@71	1334	}
dvander@71	1335	case OP_SIGN_PRI:
dvander@71	1336	{
dvander@71	1337	WriteOp_Sign_Pri(jit);
dvander@71	1338	break;
dvander@71	1339	}
dvander@71	1340	case OP_SIGN_ALT:
dvander@71	1341	{
dvander@71	1342	WriteOp_Sign_Alt(jit);
dvander@71	1343	break;
dvander@71	1344	}
dvander@71	1345	case OP_EQ:
dvander@71	1346	{
dvander@71	1347	WriteOp_Eq(jit);
dvander@71	1348	break;
dvander@71	1349	}
dvander@71	1350	case OP_NEQ:
dvander@71	1351	{
dvander@71	1352	WriteOp_Neq(jit);
dvander@71	1353	break;
dvander@71	1354	}
dvander@71	1355	case OP_LESS:
dvander@71	1356	{
dvander@71	1357	WriteOp_Less(jit);
dvander@71	1358	break;
dvander@71	1359	}
dvander@71	1360	case OP_LEQ:
dvander@71	1361	{
dvander@71	1362	WriteOp_Leq(jit);
dvander@71	1363	break;
dvander@71	1364	}
dvander@71	1365	case OP_GRTR:
dvander@71	1366	{
dvander@71	1367	WriteOp_Grtr(jit);
dvander@71	1368	break;
dvander@71	1369	}
dvander@71	1370	case OP_GEQ:
dvander@71	1371	{
dvander@71	1372	WriteOp_Geq(jit);
dvander@71	1373	break;
dvander@71	1374	}
dvander@71	1375	case OP_SLESS:
dvander@71	1376	{
dvander@71	1377	WriteOp_Sless(jit);
dvander@71	1378	break;
dvander@71	1379	}
dvander@71	1380	case OP_SLEQ:
dvander@71	1381	{
dvander@71	1382	WriteOp_Sleq(jit);
dvander@71	1383	break;
dvander@71	1384	}
dvander@71	1385	case OP_SGRTR:
dvander@71	1386	{
dvander@71	1387	WriteOp_Sgrtr(jit);
dvander@71	1388	break;
dvander@71	1389	}
dvander@71	1390	case OP_SGEQ:
dvander@71	1391	{
dvander@71	1392	WriteOp_Sgeq(jit);
dvander@71	1393	break;
dvander@71	1394	}
dvander@71	1395	case OP_EQ_C_PRI:
dvander@71	1396	{
dvander@71	1397	WriteOp_Eq_C_Pri(jit);
dvander@71	1398	break;
dvander@71	1399	}
dvander@71	1400	case OP_EQ_C_ALT:
dvander@71	1401	{
dvander@71	1402	WriteOp_Eq_C_Alt(jit);
dvander@71	1403	break;
dvander@71	1404	}
dvander@71	1405	case OP_INC_PRI:
dvander@71	1406	{
dvander@71	1407	WriteOp_Inc_Pri(jit);
dvander@71	1408	break;
dvander@71	1409	}
dvander@71	1410	case OP_INC_ALT:
dvander@71	1411	{
dvander@71	1412	WriteOp_Inc_Alt(jit);
dvander@71	1413	break;
dvander@71	1414	}
dvander@71	1415	case OP_INC:
dvander@71	1416	{
dvander@71	1417	WriteOp_Inc(jit);
dvander@71	1418	break;
dvander@71	1419	}
dvander@71	1420	case OP_INC_S:
dvander@71	1421	{
dvander@71	1422	WriteOp_Inc_S(jit);
dvander@71	1423	break;
dvander@71	1424	}
dvander@71	1425	case OP_INC_I:
dvander@71	1426	{
dvander@71	1427	WriteOp_Inc_I(jit);
dvander@71	1428	break;
dvander@71	1429	}
dvander@71	1430	case OP_DEC_PRI:
dvander@71	1431	{
dvander@71	1432	WriteOp_Dec_Pri(jit);
dvander@71	1433	break;
dvander@71	1434	}
dvander@71	1435	case OP_DEC_ALT:
dvander@71	1436	{
dvander@71	1437	WriteOp_Dec_Alt(jit);
dvander@71	1438	break;
dvander@71	1439	}
dvander@71	1440	case OP_DEC:
dvander@71	1441	{
dvander@71	1442	WriteOp_Dec(jit);
dvander@71	1443	break;
dvander@71	1444	}
dvander@71	1445	case OP_DEC_S:
dvander@71	1446	{
dvander@71	1447	WriteOp_Dec_S(jit);
dvander@71	1448	break;
dvander@71	1449	}
dvander@71	1450	case OP_DEC_I:
dvander@71	1451	{
dvander@71	1452	WriteOp_Dec_I(jit);
dvander@71	1453	break;
dvander@71	1454	}
dvander@71	1455	case OP_LOAD_PRI:
dvander@71	1456	{
dvander@71	1457	WriteOp_Load_Pri(jit);
dvander@71	1458	break;
dvander@71	1459	}
dvander@71	1460	case OP_LOAD_ALT:
dvander@71	1461	{
dvander@71	1462	WriteOp_Load_Alt(jit);
dvander@71	1463	break;
dvander@71	1464	}
dvander@71	1465	case OP_LOAD_S_PRI:
dvander@71	1466	{
dvander@71	1467	WriteOp_Load_S_Pri(jit);
dvander@71	1468	break;
dvander@71	1469	}
dvander@71	1470	case OP_LOAD_S_ALT:
dvander@71	1471	{
dvander@71	1472	WriteOp_Load_S_Alt(jit);
dvander@71	1473	break;
dvander@71	1474	}
dvander@71	1475	case OP_LREF_PRI:
dvander@71	1476	{
dvander@71	1477	WriteOp_Lref_Pri(jit);
dvander@71	1478	break;
dvander@71	1479	}
dvander@71	1480	case OP_LREF_ALT:
dvander@71	1481	{
dvander@71	1482	WriteOp_Lref_Alt(jit);
dvander@71	1483	break;
dvander@71	1484	}
dvander@71	1485	case OP_LREF_S_PRI:
dvander@71	1486	{
dvander@71	1487	WriteOp_Lref_Pri(jit);
dvander@71	1488	break;
dvander@71	1489	}
dvander@71	1490	case OP_LREF_S_ALT:
dvander@71	1491	{
dvander@71	1492	WriteOp_Lref_Alt(jit);
dvander@71	1493	break;
dvander@71	1494	}
dvander@71	1495	case OP_CONST_PRI:
dvander@71	1496	{
dvander@71	1497	WriteOp_Const_Pri(jit);
dvander@71	1498	break;
dvander@71	1499	}
dvander@71	1500	case OP_CONST_ALT:
dvander@71	1501	{
dvander@71	1502	WriteOp_Const_Alt(jit);
dvander@71	1503	break;
dvander@71	1504	}
dvander@71	1505	case OP_ADDR_PRI:
dvander@71	1506	{
dvander@71	1507	WriteOp_Addr_Pri(jit);
dvander@71	1508	break;
dvander@71	1509	}
dvander@71	1510	case OP_ADDR_ALT:
dvander@71	1511	{
dvander@71	1512	WriteOp_Addr_Alt(jit);
dvander@71	1513	break;
dvander@71	1514	}
dvander@71	1515	case OP_STOR_PRI:
dvander@71	1516	{
dvander@71	1517	WriteOp_Stor_Pri(jit);
dvander@71	1518	break;
dvander@71	1519	}
dvander@71	1520	case OP_STOR_ALT:
dvander@71	1521	{
dvander@71	1522	WriteOp_Stor_Alt(jit);
dvander@71	1523	break;
dvander@71	1524	}
dvander@71	1525	case OP_STOR_S_PRI:
dvander@71	1526	{
dvander@71	1527	WriteOp_Stor_S_Pri(jit);
dvander@71	1528	break;
dvander@71	1529	}
dvander@71	1530	case OP_STOR_S_ALT:
dvander@71	1531	{
dvander@71	1532	WriteOp_Stor_S_Alt(jit);
dvander@71	1533	break;
dvander@71	1534	}
dvander@71	1535	case OP_IDXADDR:
dvander@71	1536	{
dvander@71	1537	WriteOp_Idxaddr(jit);
dvander@71	1538	break;
dvander@71	1539	}
dvander@71	1540	case OP_SREF_PRI:
dvander@71	1541	{
dvander@71	1542	WriteOp_Sref_Pri(jit);
dvander@71	1543	break;
dvander@71	1544	}
dvander@71	1545	case OP_SREF_ALT:
dvander@71	1546	{
dvander@71	1547	WriteOp_Sref_Alt(jit);
dvander@71	1548	break;
dvander@71	1549	}
dvander@71	1550	case OP_SREF_S_PRI:
dvander@71	1551	{
dvander@71	1552	WriteOp_Sref_S_Pri(jit);
dvander@71	1553	break;
dvander@71	1554	}
dvander@71	1555	case OP_SREF_S_ALT:
dvander@71	1556	{
dvander@71	1557	WriteOp_Sref_S_Alt(jit);
dvander@71	1558	break;
dvander@71	1559	}
dvander@71	1560	case OP_ALIGN_PRI:
dvander@71	1561	{
dvander@71	1562	WriteOp_Align_Pri(jit);
dvander@71	1563	break;
dvander@71	1564	}
dvander@71	1565	case OP_ALIGN_ALT:
dvander@71	1566	{
dvander@71	1567	WriteOp_Align_Alt(jit);
dvander@71	1568	break;
dvander@71	1569	}
dvander@71	1570	case OP_POP_PRI:
dvander@71	1571	{
dvander@71	1572	WriteOp_Pop_Pri(jit);
dvander@71	1573	break;
dvander@71	1574	}
dvander@71	1575	case OP_POP_ALT:
dvander@71	1576	{
dvander@71	1577	WriteOp_Pop_Alt(jit);
dvander@71	1578	break;
dvander@71	1579	}
dvander@71	1580	case OP_SWAP_PRI:
dvander@71	1581	{
dvander@71	1582	WriteOp_Swap_Pri(jit);
dvander@71	1583	break;
dvander@71	1584	}
dvander@71	1585	case OP_SWAP_ALT:
dvander@71	1586	{
dvander@71	1587	WriteOp_Swap_Alt(jit);
dvander@71	1588	break;
dvander@71	1589	}
dvander@71	1590	case OP_PUSH_ADR:
dvander@71	1591	{
dvander@71	1592	WriteOp_PushAddr(jit);
dvander@71	1593	break;
dvander@71	1594	}
dvander@71	1595	case OP_MOVS:
dvander@71	1596	{
dvander@71	1597	WriteOp_Movs(jit);
dvander@71	1598	break;
dvander@71	1599	}
dvander@71	1600	case OP_FILL:
dvander@71	1601	{
dvander@71	1602	WriteOp_Fill(jit);
dvander@71	1603	break;
dvander@71	1604	}
dvander@71	1605	case OP_HEAP_PRI:
dvander@71	1606	{
dvander@71	1607	WriteOp_Heap_Pri(jit);
dvander@71	1608	break;
dvander@71	1609	}
dvander@71	1610	case OP_PUSH_HEAP_C:
dvander@71	1611	{
dvander@71	1612	WriteOp_Push_Heap_C(jit);
dvander@71	1613	break;
dvander@71	1614	}
dvander@71	1615	case OP_POP_HEAP_PRI:
dvander@71	1616	{
dvander@71	1617	WriteOp_Pop_Heap_Pri(jit);
dvander@71	1618	break;
dvander@71	1619	}
dvander@71	1620	case OP_PUSH_C:
dvander@71	1621	{
dvander@71	1622	WriteOp_Push_C(jit);
dvander@71	1623	break;
dvander@71	1624	}
dvander@71	1625	case OP_ZERO:
dvander@71	1626	{
dvander@71	1627	WriteOp_Zero(jit);
dvander@71	1628	break;
dvander@71	1629	}
dvander@71	1630	case OP_ZERO_S:
dvander@71	1631	{
dvander@71	1632	WriteOp_Zero_S(jit);
dvander@71	1633	break;
dvander@71	1634	}
dvander@71	1635	case OP_PUSH_PRI:
dvander@71	1636	{
dvander@71	1637	WriteOp_Push_Pri(jit);
dvander@71	1638	break;
dvander@71	1639	}
dvander@71	1640	case OP_PUSH_ALT:
dvander@71	1641	{
dvander@71	1642	WriteOp_Push_Alt(jit);
dvander@71	1643	break;
dvander@71	1644	}
dvander@72	1645	case OP_LOAD_BOTH:
dvander@72	1646	{
dvander@72	1647	WriteOp_Load_Both(jit);
dvander@72	1648	break;
dvander@72	1649	}
dvander@72	1650	case OP_LOAD_S_BOTH:
dvander@72	1651	{
dvander@72	1652	WriteOp_Load_S_Both(jit);
dvander@72	1653	break;
dvander@72	1654	}
dvander@72	1655	case OP_CONST:
dvander@72	1656	{
dvander@72	1657	WriteOp_Const(jit);
dvander@72	1658	break;
dvander@72	1659	}
dvander@72	1660	case OP_CONST_S:
dvander@72	1661	{
dvander@72	1662	WriteOp_Const_S(jit);
dvander@72	1663	break;
dvander@72	1664	}
dvander@75	1665	case OP_LOAD_I:
dvander@75	1666	{
dvander@75	1667	WriteOp_Load_I(jit);
dvander@75	1668	break;
dvander@75	1669	}
dvander@70	1670	default:
dvander@70	1671	{
dvander@72	1672	AbortCompilation(co);
dvander@72	1673	*err = SP_ERR_INVALID_INSTRUCTION;
dvander@72	1674	return NULL;
dvander@70	1675	}
dvander@70	1676	}
dvander@70	1677	}
dvander@70	1678
dvander@69	1679	*err = SP_ERR_NONE;
dvander@69	1680
dvander@69	1681	return NULL;
dvander@69	1682	}
dvander@69	1683
dvander@68	1684	const char *JITX86::GetVMName()
dvander@68	1685	{
dvander@68	1686	return "JIT (x86)";
dvander@68	1687	}
dvander@68	1688
dvander@68	1689	ICompilation JITX86::StartCompilation(sp_plugin_t plugin)
dvander@68	1690	{
dvander@68	1691	CompData *data = new CompData;
dvander@68	1692
dvander@68	1693	data->plugin = plugin;
dvander@68	1694
dvander@68	1695	return data;
dvander@68	1696	}
dvander@68	1697
dvander@68	1698	void JITX86::AbortCompilation(ICompilation *co)
dvander@68	1699	{
dvander@68	1700	delete (CompData *)co;
dvander@68	1701	}
dvander@68	1702
dvander@68	1703	bool JITX86::SetCompilationOption(ICompilation co, const char key, const char *val)
dvander@68	1704	{
dvander@68	1705	CompData data = (CompData )co;
dvander@68	1706
dvander@68	1707	if (strcmp(key, "debug") == 0)
dvander@68	1708	{
dvander@68	1709	data->debug = (atoi(val) == 1);
dvander@68	1710	if (data->debug && !(data->plugin->flags & SP_FLAG_DEBUG))
dvander@68	1711	{
dvander@68	1712	data->debug = false;
dvander@68	1713	return false;
dvander@68	1714	}
dvander@68	1715	return true;
dvander@68	1716	}
dvander@68	1717
dvander@68	1718	return false;
dvander@68	1719	}

author	David Anderson <dvander@alliedmods.net>
	Wed Sep 20 08:44:21 2006 +0000 (2006-09-20)
changeset 75	55682fa202ea
parent 74	935d64738275
child 76	0af1d530c4d3
permissions	-rw-r--r--