/**

 * vim: set ts=8 sts=2 sw=2 tw=99 et:

 * =============================================================================

 * SourcePawn JIT SDK

 * Copyright (C) 2004-2008 AlliedModders LLC.  All rights reserved.

 * =============================================================================

 *

 * This program is free software; you can redistribute it and/or modify it under

 * the terms of the GNU General Public License, version 3.0, as published by the

 * Free Software Foundation.

 * 

 * This program is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

 * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more

 * details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * As a special exception, AlliedModders LLC gives you permission to link the

 * code of this program (as well as its derivative works) to "Half-Life 2," the

 * "Source Engine," the "SourcePawn JIT," and any Game MODs that run on software

 * by the Valve Corporation.  You must obey the GNU General Public License in

 * all respects for all other code used.  Additionally, AlliedModders LLC grants

 * this exception to all derivative works.  AlliedModders LLC defines further

 * exceptions, found in LICENSE.txt (as of this writing, version JULY-31-2007),

 * or <http://www.sourcemod.net/license.php>.

 *

 * Version: $Id$

 */

#ifndef _include_sourcepawn_assembler_x86_h__

#define _include_sourcepawn_assembler_x86_h__

#include <assembler.h>

#include <ke_vector.h>

#include <string.h>

struct Register

{

  const char *name() const {

    static const char *names[] = {

      "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"

    };

    return names[code];

  }

  int code;

  bool operator == (const Register &other) const {

    return code == other.code;

  }

  bool operator != (const Register &other) const {

    return code != other.code;

  }

};

// X86 has an ancient FPU (called x87) which has a stack of registers

// numbered st0 through st7.

struct FpuRegister

{

  const char *name() const {

    static const char *names[] = {

      "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"

    };

    return names[code];

  }

  int code;

  bool operator == (const FpuRegister &other) const {

    return code == other.code;

  }

  bool operator != (const FpuRegister &other) const {

    return code != other.code;

  }

};

struct FloatRegister

{

  const char *name() const {

    static const char *names[] = {

      "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"

    };

    return names[code];

  }

  int code;

  bool operator == (const FloatRegister &other) const {

    return code == other.code;

  }

  bool operator != (const FloatRegister &other) const {

    return code != other.code;

  }

};

const Register eax = { 0 };

const Register ecx = { 1 };

const Register edx = { 2 };

const Register ebx = { 3 };

const Register esp = { 4 };

const Register ebp = { 5 };

const Register esi = { 6 };

const Register edi = { 7 };

const Register r8_al = { 0 };

const Register r8_cl = { 1 };

const Register r8_dl = { 2 };

const Register r8_bl = { 3 };

const Register r8_ah = { 4 };

const Register r8_ch = { 5 };

const Register r8_dh = { 6 };

const Register r8_bh = { 7 };

const FpuRegister st0 = { 0 };

const FpuRegister st1 = { 1 };

const FpuRegister st2 = { 2 };

const FpuRegister st3 = { 3 };

const FpuRegister st4 = { 4 };

const FpuRegister st5 = { 5 };

const FpuRegister st6 = { 6 };

const FpuRegister st7 = { 7 };

const FloatRegister xmm0 = { 0 };

const FloatRegister xmm1 = { 1 };

const FloatRegister xmm2 = { 2 };

const FloatRegister xmm3 = { 3 };

const FloatRegister xmm4 = { 4 };

const FloatRegister xmm5 = { 5 };

const FloatRegister xmm6 = { 6 };

const FloatRegister xmm7 = { 7 };

static const uint8_t kModeDisp0 = 0;

static const uint8_t kModeDisp8 = 1;

static const uint8_t kModeDisp32 = 2;

static const uint8_t kModeReg = 3;

static const uint8_t kNoIndex = 4;

static const uint8_t kSIB = 4;

static const uint8_t kRIP = 5;

enum ConditionCode {

  overflow,

  no_overflow,

  below,

  not_below,

  equal,

  not_equal,

  not_above,

  above,

  negative,

  not_negative,

  even_parity,

  odd_parity,

  less,

  not_less,

  not_greater,

  greater,

  zero = equal,

  not_zero = not_equal,

  less_equal = not_greater,

  greater_equal = not_less

};

enum Scale {

  NoScale,

  ScaleTwo,

  ScaleFour,

  ScaleEight,

  ScalePointer = ScaleFour

};

struct Operand

{

  friend class AssemblerX86;

 public:

  Operand(Register reg, int32_t disp) {

    if (reg == esp) {

      // If the reg is esp, we need a SIB encoding.

      if (disp == 0)

        sib_disp0(NoScale, kNoIndex, reg.code);

      else if (disp >= SCHAR_MIN && disp <= SCHAR_MAX)

        sib_disp8(NoScale, kNoIndex, reg.code, disp);

      else

        sib_disp32(NoScale, kNoIndex, reg.code, disp);

    } else if (disp == 0 && reg != ebp) {

      // note, [ebp+0] is disp32/rip

      modrm_disp0(reg.code);

    } else if (disp >= SCHAR_MIN && disp <= SCHAR_MAX) {

      modrm_disp8(reg.code, disp);

    } else {

      modrm_disp32(reg.code, disp);

    }

  }

  Operand(Register base, Scale scale, int32_t disp = 0) {

    if (disp == 0 && base != ebp)

      sib_disp0(scale, kNoIndex, base.code);

    else if (disp >= SCHAR_MIN && disp <= SCHAR_MAX)

      sib_disp8(scale, kNoIndex, base.code, disp);

    else

      sib_disp32(scale, kNoIndex, base.code, disp);

  }

  Operand(Register base, Register index, Scale scale, int32_t disp = 0) {

    assert(index.code != kNoIndex);

    if (disp == 0 && base != ebp)

      sib_disp0(scale, index.code, base.code);

    else if (disp >= SCHAR_MIN && disp <= SCHAR_MAX)

      sib_disp8(scale, index.code, base.code, disp);

    else

      sib_disp32(scale, index.code, base.code, disp);

  }

  explicit Operand(ExternalAddress address) {

    modrm(kModeDisp0, kRIP);

    *reinterpret_cast<const void **>(bytes_ + 1) = address.address();

  }

  bool isRegister() const {

    return mode() == kModeReg;

  }

  bool isRegister(Register r) const {

    return mode() == kModeReg && rm() == r.code;

  }

  int registerCode() const {

    return rm();

  }

  uint8_t getByte(size_t index) const {

    assert(index < length());

    return bytes_[index];

  }

  size_t length() const {

    if (mode() == kModeDisp0 && rm() == kRIP)

      return 5;

    size_t sib = (mode() != kModeReg && rm() == kSIB);

    if (mode() == kModeDisp32)

      return 5 + sib;

    if (mode() == kModeDisp8)

      return 2 + sib;

    return 1 + sib;

  }

 private:

  explicit Operand(Register reg) {

    modrm(kModeReg, reg.code);

  }

  void modrm(uint8_t mode, uint8_t rm) {

    assert(mode <= 3);

    assert(rm <= 7);

    bytes_[0] = (mode << 6) | rm;

  }

  void modrm_disp0(uint8_t rm) {

    modrm(kModeDisp0, rm);

  }

  void modrm_disp8(uint8_t rm, int8_t disp) {

    modrm(kModeDisp8, rm);

    bytes_[1] = disp;

  }

  void modrm_disp32(uint8_t rm, int32_t disp) {

    modrm(kModeDisp32, rm);

    *reinterpret_cast<int32_t *>(bytes_ + 1) = disp;

  }

  void sib(uint8_t mode, Scale scale, uint8_t index, uint8_t base) {

    modrm(mode, kSIB);

    assert(scale <= 3);

    assert(index <= 7);

    assert(base <= 7);

    bytes_[1] = (uint8_t(scale) << 6) | (index << 3) | base;

  }

  void sib_disp0(Scale scale, uint8_t index, uint8_t base) {

    sib(kModeDisp0, scale, index, base);

  }

  void sib_disp8(Scale scale, uint8_t index, uint8_t base, int8_t disp) {

    sib(kModeDisp8, scale, index, base);

    bytes_[2] = disp;

  }

  void sib_disp32(Scale scale, uint8_t index, uint8_t base, int32_t disp) {

    sib(kModeDisp32, scale, index, base);

    *reinterpret_cast<int32_t *>(bytes_ + 2) = disp;

  }

 private:

  uint8_t rm() const {

    return bytes_[0] & 7;

  }

  uint8_t mode() const {

    return bytes_[0] >> 6;

  }

 private:

  uint8_t bytes_[6];

};

class AssemblerX86 : public Assembler

{

 public:

  void movl(Register dest, Register src) {

    emit1(0x89, src.code, dest.code);

  }

  void movl(Register dest, const Operand &src) {

    emit1(0x8b, dest.code, src);

  }

  void movl(const Operand &dest, Register src) {

    emit1(0x89, src.code, dest);

  }

  void movl(Register dest, int32_t imm) {

    emit1(0xb8 + dest.code);

    writeInt32(imm);

  }

  void movl(const Operand &dest, int32_t imm) {

    if (dest.isRegister())

      emit1(0xb8 + dest.registerCode());

    else

      emit1(0xc7, 0, dest);

    writeInt32(imm);

  }

  void movw(const Operand &dest, Register src) {

    emit1(0x89, src.code, dest);

  }

  void movw(Register dest, const Operand &src) {

    emit1(0x8b, dest.code, src);

  }

  void movb(const Operand &dest, Register src) {

    emit1(0x88, src.code, dest);

  }

  void movb(Register dest, const Operand &src) {

    emit1(0x8a, dest.code, src);

  }

  void movzxb(Register dest, const Operand &src) {

    emit2(0x0f, 0xb6, dest.code, src);

  }

  void movzxb(Register dest, const Register src) {

    emit2(0x0f, 0xb6, dest.code, src.code);

  }

  void movzxw(Register dest, const Operand &src) {

    emit2(0x0f, 0xb7, dest.code, src);

  }

  void movzxw(Register dest, const Register src) {

    emit2(0x0f, 0xb7, dest.code, src.code);

  }

  void lea(Register dest, const Operand &src) {

    emit1(0x8d, dest.code, src);

  }

  void xchgl(Register dest, Register src) {

    if (src == eax)

      emit1(0x90 + dest.code);

    else if (dest == eax)

      emit1(0x90 + src.code);

    else

      emit1(0x87, src.code, dest.code);

  }

  void shll_cl(Register dest) {

    shift_cl(dest.code, 4);

  }

  void shll(Register dest, uint8_t imm) {

    shift_imm(dest.code, 4, imm);

  }

  void shll(const Operand &dest, uint8_t imm) {

    shift_imm(dest, 4, imm);

  }

  void shrl_cl(Register dest) {

    shift_cl(dest.code, 5);

  }

  void shrl(Register dest, uint8_t imm) {

    shift_imm(dest.code, 5, imm);

  }

  void shrl(const Operand &dest, uint8_t imm) {

    shift_imm(dest, 5, imm);

  }

  void sarl_cl(Register dest) {

    shift_cl(dest.code, 7);

  }

  void sarl(Register dest, uint8_t imm) {

    shift_imm(dest.code, 7, imm);

  }

  void sarl(const Operand &dest, uint8_t imm) {

    shift_imm(dest, 7, imm);

  }

  void cmpl(Register left, int32_t imm) {

    alu_imm(7, imm, Operand(left));

  }

  void cmpl(const Operand &left, int32_t imm) {

    alu_imm(7, imm, left);

  }

  void cmpl(Register left, Register right) {

    emit1(0x39, right.code, left.code);

  }

  void cmpl(const Operand &left, Register right) {

    emit1(0x39, right.code, left);

  }

  void cmpl(Register left, const Operand &right) {

    emit1(0x3b, left.code, right);

  }

  void andl(Register dest, int32_t imm) {

    alu_imm(4, imm, Operand(dest));

  }

  void andl(const Operand &dest, int32_t imm) {

    alu_imm(4, imm, dest);

  }

  void andl(Register dest, Register src) {

    emit1(0x21, src.code, dest.code);

  }

  void andl(const Operand &dest, Register src) {

    emit1(0x21, src.code, dest);

  }

  void andl(Register dest, const Operand &src) {

    emit1(0x23, dest.code, src);

  }

  void orl(Register dest, Register src) {

    emit1(0x09, src.code, dest.code);

  }

  void orl(const Operand &dest, Register src) {

    emit1(0x09, src.code, dest);

  }

  void orl(Register dest, const Operand &src) {

    emit1(0x0b, dest.code, src);

  }

  void xorl(Register dest, Register src) {

    emit1(0x31, src.code, dest.code);

  }

  void xorl(const Operand &dest, Register src) {

    emit1(0x31, src.code, dest);

  }

  void xorl(Register dest, const Operand &src) {

    emit1(0x33, dest.code, src);

  }

  void subl(Register dest, Register src) {

    emit1(0x29, src.code, dest.code);

  }

  void subl(const Operand &dest, Register src) {

    emit1(0x29, src.code, dest);

  }

  void subl(Register dest, const Operand &src) {

    emit1(0x2b, dest.code, src);

  }

  void subl(Register dest, int32_t imm) {

    alu_imm(5, imm, Operand(dest));

  }

  void subl(const Operand &dest, int32_t imm) {

    alu_imm(5, imm, dest);

  }

  void addl(Register dest, Register src) {

    emit1(0x01, src.code, dest.code);

  }

  void addl(const Operand &dest, Register src) {

    emit1(0x01, src.code, dest);

  }

  void addl(Register dest, const Operand &src) {

    emit1(0x03, dest.code, src);

  }

  void addl(Register dest, int32_t imm) {

    alu_imm(0, imm, Operand(dest));

  }

  void addl(const Operand &dest, int32_t imm) {

    alu_imm(0, imm, dest);

  }

  void imull(Register dest, const Operand &src) {

    emit2(0x0f, 0xaf, dest.code, src);

  }

  void imull(Register dest, Register src) {

    emit2(0x0f, 0xaf, dest.code, src.code);

  }

  void imull(Register dest, const Operand &src, int32_t imm) {

    if (imm >= SCHAR_MIN && imm <= SCHAR_MAX) {

      emit1(0x6b, dest.code, src);

      *pos_++ = imm;

    } else {

      emit1(0x69, dest.code, src);