sourcemod-central: public/jit/x86/x86

     1 /**

     2  * vim: set ts=4 :

     3  * ================================================================

     4  * SourcePawn (C)2004-2007 AlliedModders LLC.  All rights reserved.

     5  * ================================================================

     6  *

     7  * This file is not open source and may not be copied without explicit

     8  * written permission of AlliedModders LLC.  This file may not be redistributed

     9  * in whole or significant part.

    10  * For information, see LICENSE.txt or http://www.sourcemod.net/license.php

    11  *

    12  * Version: $Id$

    13  */

    15 #ifndef _INCLUDE_JIT_X86_MACROS_H

    16 #define _INCLUDE_JIT_X86_MACROS_H

    18 #include <limits.h>

    20 //MOD R/M

    21 #define MOD_MEM_REG	0

    22 #define MOD_DISP8	1

    23 #define MOD_DISP32	2

    24 #define MOD_REG		3

    26 //SIB

    27 #define NOSCALE		0

    28 #define	SCALE2		1

    29 #define	SCALE4		2

    30 #define SCALE8		3

    32 //Register codes

    33 #define REG_EAX			0

    34 #define REG_ECX			1

    35 #define REG_EDX			2

    36 #define REG_EBX			3

    37 #define	REG_ESP			4

    38 #define	REG_SIB			4

    39 #define REG_NOIDX		4

    40 #define REG_IMM_BASE	5

    41 #define REG_EBP			5

    42 #define REG_ESI			6

    43 #define REG_EDI			7

    45 #define IA32_16BIT_PREFIX	0x66

    47 //condition codes (for example, Jcc opcodes)

    48 #define CC_B	0x2

    49 #define CC_NAE	CC_B

    50 #define CC_NB	0x3

    51 #define CC_AE	CC_NB

    52 #define CC_E	0x4

    53 #define CC_Z	CC_E

    54 #define CC_NE	0x5

    55 #define CC_NZ	CC_NE

    56 #define CC_NA	0x6

    57 #define CC_BE	CC_NA

    58 #define CC_A	0x7

    59 #define CC_NBE	CC_A

    60 #define CC_L	0xC

    61 #define CC_NGE	CC_L

    62 #define CC_NL	0xD

    63 #define CC_GE	CC_NL

    64 #define CC_NG	0xE

    65 #define CC_LE	CC_NG

    66 #define CC_G	0xF

    67 #define CC_NLE	CC_G

    69 //Opcodes with encoding information

    70 #define IA32_XOR_RM_REG			0x31	// encoding is /r

    71 #define IA32_XOR_REG_RM			0x33	// encoding is /r

    72 #define IA32_XOR_EAX_IMM32		0x35	// encoding is /r

    73 #define IA32_XOR_RM_IMM32		0x81	// encoding is /6

    74 #define IA32_XOR_RM_IMM8		0x83	// encoding is /6

    75 #define IA32_ADD_RM_REG			0x01	// encoding is /r

    76 #define IA32_ADD_REG_RM			0x03	// encoding is /r

    77 #define IA32_ADD_RM_IMM32		0x81	// encoding is /0

    78 #define IA32_ADD_RM_IMM8		0x83	// encoding is /0

    79 #define IA32_ADD_EAX_IMM32		0x05	// no extra encoding

    80 #define IA32_SUB_RM_REG			0x29	// encoding is /r

    81 #define IA32_SUB_REG_RM			0x2B	// encoding is /r

    82 #define IA32_SUB_RM_IMM8		0x83	// encoding is /5 <imm8>

    83 #define IA32_SUB_RM_IMM32		0x81	// encoding is /5 <imm32>

    84 #define IA32_SBB_REG_RM			0x1B	// encoding is /r

    85 #define IA32_SBB_RM_IMM8		0x83	// encoding is <imm32>

    86 #define IA32_JMP_IMM32			0xE9	// encoding is imm32

    87 #define IA32_JMP_IMM8			0xEB	// encoding is imm8

    88 #define IA32_JMP_RM				0xFF	// encoding is /4

    89 #define IA32_CALL_IMM32			0xE8	// relative call, <imm32>

    90 #define IA32_CALL_RM			0xFF	// encoding is /2

    91 #define IA32_MOV_REG_IMM		0xB8	// encoding is +r <imm32>

    92 #define	IA32_MOV_RM8_REG		0x88	// encoding is /r

    93 #define	IA32_MOV_RM_REG			0x89	// encoding is /r

    94 #define	IA32_MOV_REG_RM			0x8B	// encoding is /r

    95 #define IA32_MOV_REG8_RM8		0x8A	// encoding is /r

    96 #define IA32_MOV_RM8_REG8		0x88	// encoding is /r

    97 #define IA32_MOV_RM_IMM32		0xC7	// encoding is /0

    98 #define IA32_CMP_RM_IMM32		0x81	// encoding is /7 <imm32>

    99 #define IA32_CMP_RM_IMM8		0x83	// encoding is /7 <imm8>

   100 #define IA32_CMP_AL_IMM32		0x3C	// no extra encoding

   101 #define IA32_CMP_EAX_IMM32		0x3D	// no extra encoding

   102 #define IA32_CMP_RM_REG			0x39	// encoding is /r

   103 #define IA32_CMP_REG_RM			0x3B	// encoding is /r

   104 #define IA32_CMPSB				0xA6	// no extra encoding

   105 #define IA32_TEST_RM_REG		0x85	// encoding is /r

   106 #define IA32_JCC_IMM			0x70	// encoding is +cc <imm8>

   107 #define IA32_JCC_IMM32_1		0x0F	// opcode part 1

   108 #define IA32_JCC_IMM32_2		0x80	// encoding is +cc <imm32>

   109 #define IA32_RET				0xC3	// no extra encoding

   110 #define IA32_RETN				0xC2	// encoding is <imm16>

   111 #define IA32_NEG_RM				0xF7	// encoding is /3

   112 #define IA32_INC_REG			0x40	// encoding is +r

   113 #define IA32_INC_RM				0xFF	// encoding is /0

   114 #define IA32_DEC_REG			0x48	// encoding is +r

   115 #define IA32_DEC_RM				0xFF	// encoding is /1

   116 #define IA32_OR_REG_RM			0x0B	// encoding is /r

   117 #define IA32_AND_REG_RM			0x23	// encoding is /r

   118 #define IA32_AND_EAX_IMM32		0x25	// encoding is <imm32>

   119 #define IA32_AND_RM_IMM32		0x81	// encoding is /4

   120 #define IA32_NOT_RM				0xF7	// encoding is /2

   121 #define IA32_DIV_RM				0xF7	// encoding is /6

   122 #define IA32_MUL_RM				0xF7	// encoding is /4

   123 #define IA32_IDIV_RM			0xF7	// encoding is /7

   124 #define IA32_IMUL_RM			0xF7	// encoding is /5

   125 #define IA32_IMUL_REG_IMM32		0x69	// encoding is /r

   126 #define IA32_IMUL_REG_IMM8		0x6B	// encoding is /r

   127 #define IA32_IMUL_REG_RM_1		0x0F	// encoding is _2

   128 #define IA32_IMUL_REG_RM_2		0xAF	// encoding is /r

   129 #define IA32_SHR_RM_IMM8		0xC1	// encoding is /5 <ib>

   130 #define IA32_SHR_RM_1			0xD1	// encoding is /5

   131 #define IA32_SHL_RM_IMM8		0xC1	// encoding is /4 <ib>

   132 #define IA32_SHL_RM_1			0xD1	// encoding is /4

   133 #define IA32_SAR_RM_CL			0xD3	// encoding is /7

   134 #define IA32_SAR_RM_1			0xD1	// encoding is /7

   135 #define IA32_SHR_RM_CL			0xD3	// encoding is /5

   136 #define IA32_SHL_RM_CL			0xD3	// encoding is /4

   137 #define IA32_SAR_RM_IMM8		0xC1	// encoding is /7 <ib>

   138 #define IA32_SETCC_RM8_1		0x0F	// opcode part 1

   139 #define IA32_SETCC_RM8_2		0x90	// encoding is +cc /0 (8bits)

   140 #define IA32_CMOVCC_RM_1		0x0F	// opcode part 1

   141 #define IA32_CMOVCC_RM_2		0x40	// encoding is +cc /r

   142 #define IA32_XCHG_EAX_REG		0x90	// encoding is +r

   143 #define IA32_LEA_REG_MEM		0x8D	// encoding is /r

   144 #define IA32_POP_REG			0x58	// encoding is +r

   145 #define IA32_PUSH_REG			0x50	// encoding is +r

   146 #define IA32_PUSH_RM			0xFF	// encoding is /6

   147 #define IA32_PUSH_IMM32			0x68	// encoding is <imm32>

   148 #define IA32_PUSH_IMM8			0x6A	// encoding is <imm8>

   149 #define IA32_REP				0xF3	// no extra encoding

   150 #define IA32_MOVSD				0xA5	// no extra encoding

   151 #define IA32_MOVSB				0xA4	// no extra encoding

   152 #define IA32_STOSD				0xAB	// no extra encoding

   153 #define IA32_CLD				0xFC	// no extra encoding

   154 #define IA32_PUSHAD				0x60	// no extra encoding

   155 #define IA32_POPAD				0x61	// no extra encoding

   156 #define IA32_NOP				0x90	// no extra encoding

   157 #define IA32_INT3				0xCC	// no extra encoding

   158 #define IA32_FSTP_MEM32			0xD9	// encoding is /3

   159 #define IA32_FSTP_MEM64			0xDD	// encoding is /3

   160 #define IA32_FLD_MEM32			0xD9	// encoding is /0

   161 #define IA32_FLD_MEM64			0xDD	// encoding is /0

   162 #define IA32_FILD_MEM32			0xDB	// encoding is /0

   163 #define IA32_FADD_MEM32			0xD8	// encoding is /0

   164 #define IA32_FADD_FPREG_ST0_1	0xDC	// opcode part 1

   165 #define IA32_FADD_FPREG_ST0_2	0xC0	// encoding is +r

   166 #define IA32_FSUB_MEM32			0xD8	// encoding is /4

   167 #define IA32_FMUL_MEM32			0xD8	// encoding is /1

   168 #define IA32_FDIV_MEM32			0xD8	// encoding is /6

   169 #define IA32_FSTCW_MEM16_1		0x9B	// opcode part 1

   170 #define IA32_FSTCW_MEM16_2		0xD9	// encoding is /7

   171 #define IA32_FLDCW_MEM16		0xD9	// encoding is /5

   172 #define IA32_FISTP_MEM32		0xDB	// encoding is /3

   173 #define IA32_FUCOMIP_1			0xDF	// opcode part 1

   174 #define IA32_FUCOMIP_2			0xE8	// encoding is +r

   175 #define IA32_FSTP_FPREG_1		0xDD	// opcode part 1

   176 #define IA32_FSTP_FPREG_2		0xD8	// encoding is +r

   177 #define IA32_MOVZX_R32_RM8_1	0x0F	// opcode part 1

   178 #define IA32_MOVZX_R32_RM8_2	0xB6	// encoding is /r

   179 #define IA32_MOVZX_R32_RM16_1	0x0F	// opcode part 1

   180 #define IA32_MOVZX_R32_RM16_2	0xB7	// encoding is /r

   182 inline jit_uint8_t ia32_modrm(jit_uint8_t mode, jit_uint8_t reg, jit_uint8_t rm)

   183 {

   184 	jit_uint8_t modrm = (mode << 6);

   186 	modrm |= (reg << 3);

   187 	modrm |= (rm);

   189 	return modrm;

   190 }

   192 //mode is the scaling method - NOSCALE ... SCALE8

   193 //index is the register that is scaled

   194 //base is the base register

   195 inline jit_uint8_t ia32_sib(jit_uint8_t mode, jit_uint8_t index, jit_uint8_t base)

   196 {

   197 	jit_uint8_t sib = (mode << 6);

   199 	sib |= (index << 3);

   200 	sib |= (base);

   202 	return sib;

   203 }

   205 /***********************

   206  * INCREMENT/DECREMENT *

   207  ***********************/

   209 inline void IA32_Inc_Reg(JitWriter *jit, jit_uint8_t reg)

   210 {

   211 	jit->write_ubyte(IA32_INC_REG+reg);

   212 }

   214 inline void IA32_Inc_Rm_Disp8(JitWriter *jit, jit_uint8_t reg, jit_int8_t disp)

   215 {

   216 	jit->write_ubyte(IA32_INC_RM);

   217 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, reg));

   218 	jit->write_byte(disp);

   219 }

   221 inline void IA32_Inc_Rm_Disp32(JitWriter *jit, jit_uint8_t reg, jit_int32_t disp)

   222 {

   223 	jit->write_ubyte(IA32_INC_RM);

   224 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 0, reg));

   225 	jit->write_int32(disp);

   226 }

   228 inline void IA32_Inc_Rm_Disp_Reg(JitWriter *jit, jit_uint8_t base, jit_uint8_t reg, jit_uint8_t scale)

   229 {

   230 	jit->write_ubyte(IA32_INC_RM);

   231 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, REG_SIB));

   232 	jit->write_ubyte(ia32_sib(scale, reg, base));

   233 }

   235 inline void IA32_Dec_Reg(JitWriter *jit, jit_uint8_t reg)

   236 {

   237 	jit->write_ubyte(IA32_DEC_REG+reg);

   238 }

   240 inline void IA32_Dec_Rm_Disp8(JitWriter *jit, jit_uint8_t reg, jit_int8_t disp)

   241 {

   242 	jit->write_ubyte(IA32_DEC_RM);

   243 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 1, reg));

   244 	jit->write_byte(disp);

   245 }

   247 inline void IA32_Dec_Rm_Disp32(JitWriter *jit, jit_uint8_t reg, jit_int32_t disp)

   248 {

   249 	jit->write_ubyte(IA32_DEC_RM);

   250 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 1, reg));

   251 	jit->write_int32(disp);

   252 }

   254 inline void IA32_Dec_Rm_Disp_Reg(JitWriter *jit, jit_uint8_t base, jit_uint8_t reg, jit_uint8_t scale)

   255 {

   256 	jit->write_ubyte(IA32_DEC_RM);

   257 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 1, REG_SIB));

   258 	jit->write_ubyte(ia32_sib(scale, reg, base));

   259 }

   261 /****************

   262  * BINARY LOGIC *

   263  ****************/

   265 inline void IA32_Xor_Rm_Reg(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t dest_mode)

   266 {

   267 	jit->write_ubyte(IA32_XOR_RM_REG);

   268 	jit->write_ubyte(ia32_modrm(dest_mode, src, dest));

   269 }

   271 inline void IA32_Xor_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t dest_mode)

   272 {

   273 	jit->write_ubyte(IA32_XOR_REG_RM);

   274 	jit->write_ubyte(ia32_modrm(dest_mode, dest, src));

   275 }

   277 inline void IA32_Xor_Rm_Imm8(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode, jit_int8_t value)

   278 {

   279 	jit->write_ubyte(IA32_XOR_RM_IMM8);

   280 	jit->write_ubyte(ia32_modrm(mode, 6, reg));

   281 	jit->write_byte(value);

   282 }

   284 inline void IA32_Xor_Rm_Imm32(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode, jit_int32_t value)

   285 {

   286 	jit->write_ubyte(IA32_XOR_RM_IMM32);

   287 	jit->write_ubyte(ia32_modrm(mode, 6, reg));

   288 	jit->write_int32(value);

   289 }

   291 inline void IA32_Xor_Eax_Imm32(JitWriter *jit, jit_int32_t value)

   292 {

   293 	jit->write_ubyte(IA32_XOR_EAX_IMM32);

   294 	jit->write_int32(value);

   295 }

   297 inline void IA32_Neg_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   298 {

   299 	jit->write_ubyte(IA32_NEG_RM);

   300 	jit->write_ubyte(ia32_modrm(mode, 3, reg));

   301 }

   303 inline void IA32_Or_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   304 {

   305 	jit->write_ubyte(IA32_OR_REG_RM);

   306 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   307 }

   309 inline void IA32_And_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   310 {

   311 	jit->write_ubyte(IA32_AND_REG_RM);

   312 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   313 }

   315 inline void IA32_And_Rm_Imm32(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode, jit_int32_t value)

   316 {

   317 	jit->write_ubyte(IA32_AND_RM_IMM32);

   318 	jit->write_ubyte(ia32_modrm(mode, 4, reg));

   319 	jit->write_int32(value);

   320 }

   322 inline void IA32_And_Eax_Imm32(JitWriter *jit, jit_int32_t value)

   323 {

   324 	jit->write_ubyte(IA32_AND_EAX_IMM32);

   325 	jit->write_int32(value);

   326 }

   328 inline void IA32_Not_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   329 {

   330 	jit->write_ubyte(IA32_NOT_RM);

   331 	jit->write_ubyte(ia32_modrm(mode, 2, reg));

   332 }

   334 inline void IA32_Shr_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)

   335 {

   336 	jit->write_ubyte(IA32_SHR_RM_IMM8);

   337 	jit->write_ubyte(ia32_modrm(mode, 5, dest));

   338 	jit->write_ubyte(value);

   339 }

   341 inline void IA32_Shr_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)

   342 {

   343 	jit->write_ubyte(IA32_SHR_RM_1);

   344 	jit->write_ubyte(ia32_modrm(mode, 5, dest));

   345 }

   347 inline void IA32_Shl_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)

   348 {

   349 	jit->write_ubyte(IA32_SHL_RM_IMM8);

   350 	jit->write_ubyte(ia32_modrm(mode, 4, dest));

   351 	jit->write_ubyte(value);

   352 }

   354 inline void IA32_Shl_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)

   355 {

   356 	jit->write_ubyte(IA32_SHL_RM_1);

   357 	jit->write_ubyte(ia32_modrm(mode, 4, dest));

   358 }

   360 inline void IA32_Sar_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t value, jit_uint8_t mode)

   361 {

   362 	jit->write_ubyte(IA32_SAR_RM_IMM8);

   363 	jit->write_ubyte(ia32_modrm(mode, 7, dest));

   364 	jit->write_ubyte(value);

   365 }

   367 inline void IA32_Sar_Rm_CL(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   368 {

   369 	jit->write_ubyte(IA32_SAR_RM_CL);

   370 	jit->write_ubyte(ia32_modrm(mode, 7, reg));

   371 }

   373 inline void IA32_Sar_Rm_1(JitWriter *jit, jit_uint8_t dest, jit_uint8_t mode)

   374 {

   375 	jit->write_ubyte(IA32_SAR_RM_1);

   376 	jit->write_ubyte(ia32_modrm(mode, 7, dest));

   377 }

   379 inline void IA32_Shr_Rm_CL(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   380 {

   381 	jit->write_ubyte(IA32_SHR_RM_CL);

   382 	jit->write_ubyte(ia32_modrm(mode, 5, reg));

   383 }

   385 inline void IA32_Shl_Rm_CL(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   386 {

   387 	jit->write_ubyte(IA32_SHL_RM_CL);

   388 	jit->write_ubyte(ia32_modrm(mode, 4, reg));

   389 }

   391 inline void IA32_Xchg_Eax_Reg(JitWriter *jit, jit_uint8_t reg)

   392 {

   393 	jit->write_ubyte(IA32_XCHG_EAX_REG+reg);

   394 }

   396 /**********************

   397  * ARITHMETIC (BASIC) *

   398  **********************/

   400 inline void IA32_Add_Rm_Reg(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   401 {

   402 	jit->write_ubyte(IA32_ADD_RM_REG);

   403 	jit->write_ubyte(ia32_modrm(mode, src, dest));

   404 }

   406 inline void IA32_Add_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   407 {

   408 	jit->write_ubyte(IA32_ADD_REG_RM);

   409 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   410 }

   412 inline void IA32_Add_Rm_Imm8(JitWriter *jit, jit_uint8_t reg, jit_int8_t value, jit_uint8_t mode)

   413 {

   414 	jit->write_ubyte(IA32_ADD_RM_IMM8);

   415 	jit->write_ubyte(ia32_modrm(mode, 0, reg));

   416 	jit->write_byte(value);

   417 }

   419 inline void IA32_Add_Rm_Imm32(JitWriter *jit, jit_uint8_t reg, jit_int32_t value, jit_uint8_t mode)

   420 {

   421 	jit->write_ubyte(IA32_ADD_RM_IMM32);

   422 	jit->write_ubyte(ia32_modrm(mode, 0, reg));

   423 	jit->write_int32(value);

   424 }

   426 inline void IA32_Add_Eax_Imm32(JitWriter *jit, jit_int32_t value)

   427 {

   428 	jit->write_ubyte(IA32_ADD_EAX_IMM32);

   429 	jit->write_int32(value);

   430 }

   432 inline void IA32_Sub_Rm_Reg(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   433 {

   434 	jit->write_ubyte(IA32_SUB_RM_REG);

   435 	jit->write_ubyte(ia32_modrm(mode, src, dest));

   436 }

   438 inline void IA32_Sub_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   439 {

   440 	jit->write_ubyte(IA32_SUB_REG_RM);

   441 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   442 }

   444 inline void IA32_Sub_Reg_Rm_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp8)

   445 {

   446 	jit->write_ubyte(IA32_SUB_REG_RM);

   447 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

   448 	jit->write_byte(disp8);

   449 }

   451 inline void IA32_Sub_Rm_Reg_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp8)

   452 {

   453 	jit->write_ubyte(IA32_SUB_RM_REG);

   454 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, dest));

   455 	jit->write_byte(disp8);

   456 }

   458 inline void IA32_Sub_Rm_Imm8(JitWriter *jit, jit_uint8_t reg, jit_int8_t val, jit_uint8_t mode)

   459 {

   460 	jit->write_ubyte(IA32_SUB_RM_IMM8);

   461 	jit->write_ubyte(ia32_modrm(mode, 5, reg));

   462 	jit->write_byte(val);

   463 }

   465 inline void IA32_Sub_Rm_Imm32(JitWriter *jit, jit_uint8_t reg, jit_int32_t val, jit_uint8_t mode)

   466 {

   467 	jit->write_ubyte(IA32_SUB_RM_IMM32);

   468 	jit->write_ubyte(ia32_modrm(mode, 5, reg));

   469 	jit->write_int32(val);

   470 }

   472 inline void IA32_Sbb_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   473 {

   474 	jit->write_ubyte(IA32_SBB_REG_RM);

   475 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   476 }

   478 inline void IA32_Sbb_Rm_Imm8(JitWriter *jit, jit_uint8_t dest, jit_int8_t value, jit_uint8_t mode)

   479 {

   480 	jit->write_ubyte(IA32_SBB_RM_IMM8);

   481 	jit->write_ubyte(ia32_modrm(mode, 3, dest));

   482 	jit->write_byte(value);

   483 }

   485 inline void IA32_Div_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   486 {

   487 	jit->write_ubyte(IA32_DIV_RM);

   488 	jit->write_ubyte(ia32_modrm(mode, 6, reg));

   489 }

   491 inline void IA32_IDiv_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   492 {

   493 	jit->write_ubyte(IA32_IDIV_RM);

   494 	jit->write_ubyte(ia32_modrm(mode, 7, reg));

   495 }

   497 inline void IA32_Mul_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   498 {

   499 	jit->write_ubyte(IA32_MUL_RM);

   500 	jit->write_ubyte(ia32_modrm(mode, 4, reg));

   501 }

   503 inline void IA32_IMul_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

   504 {

   505 	jit->write_ubyte(IA32_IMUL_RM);

   506 	jit->write_ubyte(ia32_modrm(mode, 5, reg));

   507 }

   509 inline void IA32_IMul_Reg_Imm8(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode, jit_int8_t value)

   510 {

   511 	jit->write_ubyte(IA32_IMUL_REG_IMM8);

   512 	jit->write_ubyte(ia32_modrm(mode, 0, reg));

   513 	jit->write_byte(value);

   514 }

   516 inline void IA32_IMul_Reg_Imm32(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode, jit_int32_t value)

   517 {

   518 	jit->write_ubyte(IA32_IMUL_REG_IMM32);

   519 	jit->write_ubyte(ia32_modrm(mode, 0, reg));

   520 	jit->write_int32(value);

   521 }

   523 inline void IA32_IMul_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   524 {

   525 	jit->write_ubyte(IA32_IMUL_REG_RM_1);

   526 	jit->write_ubyte(IA32_IMUL_REG_RM_2);

   527 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   528 }

   530 inline void IA32_Add_Rm_Reg_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

   531 {

   532 	jit->write_ubyte(IA32_ADD_RM_REG);

   533 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, dest));

   534 	jit->write_byte(disp);

   535 }

   537 inline void IA32_Add_Reg_Rm_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

   538 {

   539 	jit->write_ubyte(IA32_ADD_REG_RM);

   540 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

   541 	jit->write_byte(disp);

   542 }

   544 inline void IA32_Add_Rm_Imm8_Disp8(JitWriter *jit,

   545 							 jit_uint8_t dest,

   546 							 jit_int8_t val,

   547 							 jit_int8_t disp8)

   548 {

   549 	jit->write_ubyte(IA32_ADD_RM_IMM8);

   550 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, dest));

   551 	jit->write_byte(disp8);

   552 	jit->write_byte(val);

   553 }

   555 inline void IA32_Add_Rm_Imm32_Disp8(JitWriter *jit,

   556 							 jit_uint8_t dest,

   557 							 jit_int32_t val,

   558 							 jit_int8_t disp8)

   559 {

   560 	jit->write_ubyte(IA32_ADD_RM_IMM32);

   561 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, dest));

   562 	jit->write_byte(disp8);

   563 	jit->write_int32(val);

   564 }

   566 inline jitoffs_t IA32_Add_Rm_Imm32_Later(JitWriter *jit,

   567 									jit_uint8_t dest,

   568 									jit_uint8_t mode)

   569 {

   570 	jit->write_ubyte(IA32_ADD_RM_IMM32);

   571 	jit->write_ubyte(ia32_modrm(mode, 0, dest));

   572 	jitoffs_t ptr = jit->get_outputpos();

   573 	jit->write_int32(0);

   574 	return ptr;

   575 }

   577 inline void IA32_Add_Rm_Imm8_Disp32(JitWriter *jit,

   578 							jit_uint8_t dest,

   579 							jit_int8_t val,

   580 							jit_int32_t disp32)

   581 {

   582 	jit->write_ubyte(IA32_ADD_RM_IMM8);

   583 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 0, dest));

   584 	jit->write_int32(disp32);

   585 	jit->write_byte(val);

   586 }

   588 inline void IA32_Add_RmEBP_Imm8_Disp_Reg(JitWriter *jit,

   589 								jit_uint8_t dest_base,

   590 								jit_uint8_t dest_index,

   591 								jit_uint8_t dest_scale,

   592 								jit_int8_t val)

   593 {

   594 	jit->write_ubyte(IA32_ADD_RM_IMM8);

   595 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, REG_SIB));

   596 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   597 	jit->write_byte(0);

   598 	jit->write_byte(val);

   599 }

   601 inline void IA32_Sub_Rm_Imm8_Disp8(JitWriter *jit,

   602 							jit_uint8_t dest,

   603 							jit_int8_t val,

   604 							jit_int8_t disp8)

   605 {

   606 	jit->write_ubyte(IA32_SUB_RM_IMM8);

   607 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 5, dest));

   608 	jit->write_byte(disp8);

   609 	jit->write_byte(val);

   610 }

   612 inline void IA32_Sub_Rm_Imm8_Disp32(JitWriter *jit,

   613 							 jit_uint8_t dest,

   614 							 jit_int8_t val,

   615 							 jit_int32_t disp32)

   616 {

   617 	jit->write_ubyte(IA32_SUB_RM_IMM8);

   618 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 5, dest));

   619 	jit->write_int32(disp32);

   620 	jit->write_byte(val);

   621 }

   623 inline void IA32_Sub_RmEBP_Imm8_Disp_Reg(JitWriter *jit,

   624 							   jit_uint8_t dest_base,

   625 							   jit_uint8_t dest_index,

   626 							   jit_uint8_t dest_scale,

   627 							   jit_int8_t val)

   628 {

   629 	jit->write_ubyte(IA32_SUB_RM_IMM8);

   630 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 5, REG_SIB));

   631 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   632 	jit->write_byte(0);

   633 	jit->write_byte(val);

   634 }

   636 /**

   637 * Memory Instructions

   638 */

   640 inline void IA32_Lea_Reg_DispRegMult(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src_base, jit_uint8_t src_index, jit_uint8_t scale)

   641 {

   642 	jit->write_ubyte(IA32_LEA_REG_MEM);

   643 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, dest, REG_SIB));

   644 	jit->write_ubyte(ia32_sib(scale, src_index, src_base));

   645 }

   647 inline void IA32_Lea_Reg_DispEBPRegMult(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src_base, jit_uint8_t src_index, jit_uint8_t scale)

   648 {

   649 	jit->write_ubyte(IA32_LEA_REG_MEM);

   650 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, REG_SIB));

   651 	jit->write_ubyte(ia32_sib(scale, src_index, src_base));

   652 	jit->write_byte(0);

   653 }

   655 inline void IA32_Lea_Reg_DispRegMultImm8(JitWriter *jit,

   656 							  jit_uint8_t dest,

   657 							  jit_uint8_t src_base,

   658 							  jit_uint8_t src_index,

   659 							  jit_uint8_t scale,

   660 							  jit_int8_t val)

   661 {

   662 	jit->write_ubyte(IA32_LEA_REG_MEM);

   663 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, REG_SIB));

   664 	jit->write_ubyte(ia32_sib(scale, src_index, src_base));

   665 	jit->write_byte(val);

   666 }

   668 inline void IA32_Lea_Reg_DispRegMultImm32(JitWriter *jit,

   669 										 jit_uint8_t dest,

   670 										 jit_uint8_t src_base,

   671 										 jit_uint8_t src_index,

   672 										 jit_uint8_t scale,

   673 										 jit_int32_t val)

   674 {

   675 	jit->write_ubyte(IA32_LEA_REG_MEM);

   676 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, REG_SIB));

   677 	jit->write_ubyte(ia32_sib(scale, src_index, src_base));

   678 	jit->write_int32(val);

   679 }

   681 inline void IA32_Lea_Reg_RegMultImm32(JitWriter *jit,

   682 										jit_uint8_t dest,

   683 										jit_uint8_t src_index,

   684 										jit_uint8_t scale,

   685 										jit_int32_t val)

   686 {

   687 	jit->write_ubyte(IA32_LEA_REG_MEM);

   688 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, dest, REG_SIB));

   689 	jit->write_ubyte(ia32_sib(scale, src_index, REG_IMM_BASE));

   690 	jit->write_int32(val);

   691 }

   693 inline void IA32_Lea_DispRegImm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src_base, jit_int8_t val)

   694 {

   695 	jit->write_ubyte(IA32_LEA_REG_MEM);

   696 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src_base));

   697 	jit->write_byte(val);

   698 }

   700 inline void IA32_Lea_DispRegImm32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src_base, jit_int32_t val)

   701 {

   702 	jit->write_ubyte(IA32_LEA_REG_MEM);

   703 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, src_base));

   704 	jit->write_int32(val);

   705 }

   707 /**

   708 * Stack Instructions

   709 */

   711 inline void IA32_Pop_Reg(JitWriter *jit, jit_uint8_t reg)

   712 {

   713 	jit->write_ubyte(IA32_POP_REG+reg);

   714 }

   716 inline void IA32_Push_Reg(JitWriter *jit, jit_uint8_t reg)

   717 {

   718 	jit->write_ubyte(IA32_PUSH_REG+reg);

   719 }

   721 inline void IA32_Push_Imm8(JitWriter *jit, jit_int8_t val)

   722 {

   723 	jit->write_ubyte(IA32_PUSH_IMM8);

   724 	jit->write_byte(val);

   725 }

   727 inline void IA32_Push_Imm32(JitWriter *jit, jit_int32_t val)

   728 {

   729 	jit->write_ubyte(IA32_PUSH_IMM32);

   730 	jit->write_int32(val);

   731 }

   733 inline void IA32_Pushad(JitWriter *jit)

   734 {

   735 	jit->write_ubyte(IA32_PUSHAD);

   736 }

   738 inline void IA32_Popad(JitWriter *jit)

   739 {

   740 	jit->write_ubyte(IA32_POPAD);

   741 }

   743 inline void IA32_Push_Rm_Disp8(JitWriter *jit, jit_uint8_t reg, jit_int8_t disp8)

   744 {

   745 	jit->write_ubyte(IA32_PUSH_RM);

   746 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 6, reg));

   747 	jit->write_byte(disp8);

   748 }

   750 inline void IA32_Push_Rm_Disp8_ESP(JitWriter *jit, jit_int8_t disp8)

   751 {

   752 	jit->write_ubyte(IA32_PUSH_RM);

   753 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 6, REG_SIB));

   754 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

   755 	jit->write_byte(disp8);

   756 }

   758 /**

   759  * Moving from REGISTER/MEMORY to REGISTER

   760  */

   762 inline void IA32_Mov_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   763 {

   764 	jit->write_ubyte(IA32_MOV_REG_RM);

   765 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   766 }

   768 inline void IA32_Mov_Reg8_Rm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   769 {

   770 	jit->write_ubyte(IA32_MOV_REG8_RM8);

   771 	jit->write_ubyte(ia32_modrm(mode, dest, src));

   772 }

   774 inline void IA32_Mov_Reg_RmESP(JitWriter *jit, jit_uint8_t dest)

   775 {

   776 	jit->write_ubyte(IA32_MOV_REG_RM);

   777 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, dest, REG_ESP));

   778 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

   779 }

   781 inline void IA32_Mov_Reg_Rm_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

   782 {

   783 	jit->write_ubyte(IA32_MOV_REG_RM);

   784 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

   785 	jit->write_byte(disp);

   786 }

   788 inline void IA32_Mov_Reg8_Rm8_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

   789 {

   790 	jit->write_ubyte(IA32_MOV_REG8_RM8);

   791 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

   792 	jit->write_byte(disp);

   793 }

   795 inline void IA32_Mov_Reg_Esp_Disp8(JitWriter *jit, jit_uint8_t dest, jit_int8_t disp)

   796 {

   797 	jit->write_ubyte(IA32_MOV_REG_RM);

   798 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, REG_SIB));

   799 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

   800 	jit->write_byte(disp);

   801 }

   803 inline void IA32_Mov_Reg_Rm_Disp32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int32_t disp)

   804 {

   805 	jit->write_ubyte(IA32_MOV_REG_RM);

   806 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, src));

   807 	jit->write_int32(disp);

   808 }

   810 inline void IA32_Mov_Reg8_Rm8_Disp32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int32_t disp)

   811 {

   812 	jit->write_ubyte(IA32_MOV_REG8_RM8);

   813 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, src));

   814 	jit->write_int32(disp);

   815 }

   817 inline void IA32_Mov_Reg_Rm_Disp_Reg(JitWriter *jit,

   818 							jit_uint8_t dest,

   819 							jit_uint8_t src_base,

   820 							jit_uint8_t src_index,

   821 							jit_uint8_t src_scale)

   822 {

   823 	jit->write_ubyte(IA32_MOV_REG_RM);

   824 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, dest, REG_SIB));

   825 	jit->write_ubyte(ia32_sib(src_scale, src_index, src_base));

   826 }

   828 inline void IA32_Mov_Reg_Rm_Disp_Reg_Disp8(JitWriter *jit,

   829 									 jit_uint8_t dest,

   830 									 jit_uint8_t src_base,

   831 									 jit_uint8_t src_index,

   832 									 jit_uint8_t src_scale,

   833 									 jit_int8_t disp8)

   834 {

   835 	jit->write_ubyte(IA32_MOV_REG_RM);

   836 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, REG_SIB));

   837 	jit->write_ubyte(ia32_sib(src_scale, src_index, src_base));

   838 	jit->write_byte(disp8);

   839 }

   841 inline void IA32_Mov_Reg_RmEBP_Disp_Reg(JitWriter *jit,

   842 									 jit_uint8_t dest,

   843 									 jit_uint8_t src_base,

   844 									 jit_uint8_t src_index,

   845 									 jit_uint8_t src_scale)

   846 {

   847 	jit->write_ubyte(IA32_MOV_REG_RM);

   848 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, REG_SIB));

   849 	jit->write_ubyte(ia32_sib(src_scale, src_index, src_base));

   850 	jit->write_byte(0);

   851 }

   853 /**

   854  * Moving from REGISTER to REGISTER/MEMORY

   855  */

   857 inline void IA32_Mov_Rm_Reg(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   858 {

   859 	jit->write_ubyte(IA32_MOV_RM_REG);

   860 	jit->write_ubyte(ia32_modrm(mode, src, dest));

   861 }

   863 inline void IA32_Mov_Rm8_Reg8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

   864 {

   865 	jit->write_ubyte(IA32_MOV_RM8_REG8);

   866 	jit->write_ubyte(ia32_modrm(mode, src, dest));

   867 }

   869 inline void IA32_Mov_RmESP_Reg(JitWriter *jit, jit_uint8_t src)

   870 {

   871 	jit->write_ubyte(IA32_MOV_RM_REG);

   872 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, src, REG_ESP));

   873 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

   874 }

   876 inline void IA32_Mov_Rm_Reg_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

   877 {

   878 	jit->write_ubyte(IA32_MOV_RM_REG);

   879 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, dest));

   880 	jit->write_byte(disp);

   881 }

   883 inline void IA32_Mov_Rm_Reg_Disp32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int32_t disp)

   884 {

   885 	jit->write_ubyte(IA32_MOV_RM_REG);

   886 	jit->write_ubyte(ia32_modrm(MOD_DISP32, src, dest));

   887 	jit->write_int32(disp);

   888 }

   890 inline void IA32_Mov_RmEBP_Reg_Disp_Reg(JitWriter *jit,

   891 							  jit_uint8_t dest_base,

   892 							  jit_uint8_t dest_index,

   893 							  jit_uint8_t dest_scale,

   894 							  jit_uint8_t src)

   895 {

   896 	jit->write_ubyte(IA32_MOV_RM_REG);

   897 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, REG_SIB));

   898 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   899 	jit->write_byte(0);

   900 }

   902 inline void IA32_Mov_Rm8EBP_Reg_Disp_Reg(JitWriter *jit,

   903 									 jit_uint8_t dest_base,

   904 									 jit_uint8_t dest_index,

   905 									 jit_uint8_t dest_scale,

   906 									 jit_uint8_t src)

   907 {

   908 	jit->write_ubyte(IA32_MOV_RM8_REG);

   909 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, REG_SIB));

   910 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   911 	jit->write_byte(0);

   912 }

   914 inline void IA32_Mov_Rm16EBP_Reg_Disp_Reg(JitWriter *jit,

   915 									  jit_uint8_t dest_base,

   916 									  jit_uint8_t dest_index,

   917 									  jit_uint8_t dest_scale,

   918 									  jit_uint8_t src)

   919 {

   920 	jit->write_ubyte(IA32_16BIT_PREFIX);

   921 	jit->write_ubyte(IA32_MOV_RM_REG);

   922 	jit->write_ubyte(ia32_modrm(MOD_DISP8, src, REG_SIB));

   923 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   924 	jit->write_byte(0);

   925 }

   927 /**

   928  * Moving from IMMEDIATE to REGISTER

   929  */

   931 inline jitoffs_t IA32_Mov_Reg_Imm32(JitWriter *jit, jit_uint8_t dest, jit_int32_t num)

   932 {

   933 	jitoffs_t offs;

   934 	jit->write_ubyte(IA32_MOV_REG_IMM+dest);

   935 	offs = jit->get_outputpos();

   936 	jit->write_int32(num);

   937 	return offs;

   938 }

   940 inline void IA32_Mov_Rm_Imm32(JitWriter *jit, jit_uint8_t dest, jit_int32_t val, jit_uint8_t mode)

   941 {

   942 	jit->write_ubyte(IA32_MOV_RM_IMM32);

   943 	jit->write_ubyte(ia32_modrm(mode, 0, dest));

   944 	jit->write_int32(val);

   945 }

   947 inline void IA32_Mov_Rm_Imm32_Disp8(JitWriter *jit,

   948 							 jit_uint8_t dest,

   949 							 jit_int32_t val,

   950 							 jit_int8_t disp8)

   951 {

   952 	jit->write_ubyte(IA32_MOV_RM_IMM32);

   953 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, dest));

   954 	jit->write_byte(disp8);

   955 	jit->write_int32(val);

   956 }

   958 inline void IA32_Mov_Rm_Imm32_Disp32(JitWriter *jit,

   959 							 jit_uint8_t dest,

   960 							 jit_int32_t val,

   961 							 jit_int32_t disp32)

   962 {

   963 	jit->write_ubyte(IA32_MOV_RM_IMM32);

   964 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 0, dest));

   965 	jit->write_int32(disp32);

   966 	jit->write_int32(val);

   967 }

   969 inline void IA32_Mov_RmEBP_Imm32_Disp_Reg(JitWriter *jit,

   970 								jit_uint8_t dest_base,

   971 								jit_uint8_t dest_index,

   972 								jit_uint8_t dest_scale,

   973 								jit_int32_t val)

   974 {

   975 	jit->write_ubyte(IA32_MOV_RM_IMM32);

   976 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, REG_SIB));

   977 	jit->write_ubyte(ia32_sib(dest_scale, dest_index, dest_base));

   978 	jit->write_byte(0);

   979 	jit->write_int32(val);

   980 }

   982 inline void IA32_Mov_ESP_Disp8_Imm32(JitWriter *jit, jit_int8_t disp8, jit_int32_t val)

   983 {

   984 	jit->write_ubyte(IA32_MOV_RM_IMM32);

   985 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, REG_SIB));

   986 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

   987 	jit->write_byte(disp8);

   988 	jit->write_int32(val);

   989 }

   991 /**

   992 * Floating Point Instructions

   993 */

   995 inline void IA32_Fstcw_Mem16_ESP(JitWriter *jit)

   996 {

   997 	jit->write_ubyte(IA32_FSTCW_MEM16_1);

   998 	jit->write_ubyte(IA32_FSTCW_MEM16_2);

   999 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 7, REG_SIB));

  1000 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1001 }

  1003 inline void IA32_Fldcw_Mem16_ESP(JitWriter *jit)

  1004 {

  1005 	jit->write_ubyte(IA32_FLDCW_MEM16);

  1006 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 5, REG_SIB));

  1007 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1008 }

  1010 inline void IA32_Fldcw_Mem16_Disp8_ESP(JitWriter *jit, jit_int8_t disp8)

  1011 {

  1012 	jit->write_ubyte(IA32_FLDCW_MEM16);

  1013 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 5, REG_SIB));

  1014 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1015 	jit->write_byte(disp8);

  1016 }

  1018 inline void IA32_Fistp_Mem32_ESP(JitWriter *jit)

  1019 {

  1020 	jit->write_ubyte(IA32_FISTP_MEM32);

  1021 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 3, REG_SIB));

  1022 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1023 }

  1025 inline void IA32_Fistp_Mem32_Disp8_Esp(JitWriter *jit, jit_int8_t disp8)

  1026 {

  1027 	jit->write_ubyte(IA32_FISTP_MEM32);

  1028 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 3, REG_SIB));

  1029 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1030 	jit->write_byte(disp8);

  1031 }

  1033 inline void IA32_Fucomip_ST0_FPUreg(JitWriter *jit, jit_uint8_t reg)

  1034 {

  1035 	jit->write_ubyte(IA32_FUCOMIP_1);

  1036 	jit->write_ubyte(IA32_FUCOMIP_2+reg);

  1037 }

  1039 inline void IA32_Fadd_FPUreg_ST0(JitWriter *jit, jit_uint8_t reg)

  1040 {

  1041 	jit->write_ubyte(IA32_FADD_FPREG_ST0_1);

  1042 	jit->write_ubyte(IA32_FADD_FPREG_ST0_2+reg);

  1043 }

  1045 inline void IA32_Fadd_Mem32_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1046 {

  1047 	jit->write_ubyte(IA32_FADD_MEM32);

  1048 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, src));

  1049 	jit->write_byte(val);

  1050 }

  1052 inline void IA32_Fadd_Mem32_ESP(JitWriter *jit)

  1053 {

  1054 	jit->write_ubyte(IA32_FADD_MEM32);

  1055 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, REG_SIB));

  1056 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1057 }

  1059 inline void IA32_Fsub_Mem32_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1060 {

  1061 	jit->write_ubyte(IA32_FSUB_MEM32);

  1062 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 4, src));

  1063 	jit->write_byte(val);

  1064 }

  1066 inline void IA32_Fmul_Mem32_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1067 {

  1068 	jit->write_ubyte(IA32_FMUL_MEM32);

  1069 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 1, src));

  1070 	jit->write_byte(val);

  1071 }

  1073 inline void IA32_Fdiv_Mem32_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1074 {

  1075 	jit->write_ubyte(IA32_FDIV_MEM32);

  1076 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 6, src));

  1077 	jit->write_byte(val);

  1078 }

  1080 inline void IA32_Fild_Mem32(JitWriter *jit, jit_uint8_t src)

  1081 {

  1082 	jit->write_ubyte(IA32_FILD_MEM32);

  1083 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, src));

  1084 }

  1086 inline void IA32_Fstp_Mem32(JitWriter *jit, jit_uint8_t dest)

  1087 {

  1088 	jit->write_ubyte(IA32_FSTP_MEM32);

  1089 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 3, dest));

  1090 }

  1092 inline void IA32_Fstp_Mem64(JitWriter *jit, jit_uint8_t dest)

  1093 {

  1094 	jit->write_ubyte(IA32_FSTP_MEM64);

  1095 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 3, dest));

  1096 }

  1098 inline void IA32_Fstp_Mem32_ESP(JitWriter *jit)

  1099 {

  1100 	jit->write_ubyte(IA32_FSTP_MEM32);

  1101 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 3, REG_SIB));

  1102 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1103 }

  1105 inline void IA32_Fstp_Mem64_ESP(JitWriter *jit)

  1106 {

  1107 	jit->write_ubyte(IA32_FSTP_MEM64);

  1108 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 3, REG_SIB));

  1109 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1110 }

  1112 inline void IA32_Fstp_FPUreg(JitWriter *jit, jit_uint8_t reg)

  1113 {

  1114 	jit->write_ubyte(IA32_FSTP_FPREG_1);

  1115 	jit->write_ubyte(IA32_FSTP_FPREG_2+reg);

  1116 }

  1118 inline void IA32_Fld_Mem32(JitWriter *jit, jit_uint8_t src)

  1119 {

  1120 	jit->write_ubyte(IA32_FLD_MEM32);

  1121 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, src));

  1122 }

  1124 inline void IA32_Fld_Mem64(JitWriter *jit, jit_uint8_t src)

  1125 {

  1126 	jit->write_ubyte(IA32_FLD_MEM64);

  1127 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, src));

  1128 }

  1130 inline void IA32_Fld_Mem32_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1131 {

  1132 	jit->write_ubyte(IA32_FLD_MEM32);

  1133 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, src));

  1134 	jit->write_byte(val);

  1135 }

  1137 inline void IA32_Fld_Mem64_Disp8(JitWriter *jit, jit_uint8_t src, jit_int8_t val)

  1138 {

  1139 	jit->write_ubyte(IA32_FLD_MEM64);

  1140 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, src));

  1141 	jit->write_byte(val);

  1142 }

  1144 inline void IA32_Fld_Mem32_Disp32(JitWriter *jit, jit_uint8_t src, jit_int32_t val)

  1145 {

  1146 	jit->write_ubyte(IA32_FLD_MEM32);

  1147 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 0, src));

  1148 	jit->write_int32(val);

  1149 }

  1151 inline void IA32_Fld_Mem64_Disp32(JitWriter *jit, jit_uint8_t src, jit_int32_t val)

  1152 {

  1153 	jit->write_ubyte(IA32_FLD_MEM64);

  1154 	jit->write_ubyte(ia32_modrm(MOD_DISP32, 0, src));

  1155 	jit->write_int32(val);

  1156 }

  1158 /**

  1159 * Move data with zero extend

  1160 */

  1162 inline void IA32_Movzx_Reg32_Rm8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

  1163 {

  1164 	jit->write_ubyte(IA32_MOVZX_R32_RM8_1);

  1165 	jit->write_ubyte(IA32_MOVZX_R32_RM8_2);

  1166 	jit->write_ubyte(ia32_modrm(mode, dest, src));

  1167 }

  1169 inline void IA32_Movzx_Reg32_Rm8_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

  1170 {

  1171 	jit->write_ubyte(IA32_MOVZX_R32_RM8_1);

  1172 	jit->write_ubyte(IA32_MOVZX_R32_RM8_2);

  1173 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

  1174 	jit->write_byte(disp);

  1175 }

  1177 inline void IA32_Movzx_Reg32_Rm8_Disp32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int32_t disp)

  1178 {

  1179 	jit->write_ubyte(IA32_MOVZX_R32_RM8_1);

  1180 	jit->write_ubyte(IA32_MOVZX_R32_RM8_2);

  1181 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, src));

  1182 	jit->write_int32(disp);

  1183 }

  1185 inline void IA32_Movzx_Reg32_Rm16(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

  1186 {

  1187 	jit->write_ubyte(IA32_MOVZX_R32_RM16_1);

  1188 	jit->write_ubyte(IA32_MOVZX_R32_RM16_2);

  1189 	jit->write_ubyte(ia32_modrm(mode, dest, src));

  1190 }

  1192 inline void IA32_Movzx_Reg32_Rm16_Disp8(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int8_t disp)

  1193 {

  1194 	jit->write_ubyte(IA32_MOVZX_R32_RM16_1);

  1195 	jit->write_ubyte(IA32_MOVZX_R32_RM16_2);

  1196 	jit->write_ubyte(ia32_modrm(MOD_DISP8, dest, src));

  1197 	jit->write_byte(disp);

  1198 }

  1200 inline void IA32_Movzx_Reg32_Rm16_Disp32(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_int32_t disp)

  1201 {

  1202 	jit->write_ubyte(IA32_MOVZX_R32_RM16_1);

  1203 	jit->write_ubyte(IA32_MOVZX_R32_RM16_2);

  1204 	jit->write_ubyte(ia32_modrm(MOD_DISP32, dest, src));

  1205 	jit->write_int32(disp);

  1206 }

  1208 /**

  1209  * Branching/Jumping

  1210  */

  1212 inline jitoffs_t IA32_Jump_Cond_Imm8(JitWriter *jit, jit_uint8_t cond, jit_int8_t disp)

  1213 {

  1214 	jitoffs_t ptr;

  1215 	jit->write_ubyte(IA32_JCC_IMM+cond);

  1216 	ptr = jit->get_outputpos();

  1217 	jit->write_byte(disp);

  1218 	return ptr;

  1219 }

  1221 inline jitoffs_t IA32_Jump_Imm32(JitWriter *jit, jit_int32_t disp)

  1222 {

  1223 	jitoffs_t ptr;

  1224 	jit->write_ubyte(IA32_JMP_IMM32);

  1225 	ptr = jit->get_outputpos();

  1226 	jit->write_int32(disp);

  1227 	return ptr;

  1228 }

  1230 inline jitoffs_t IA32_Jump_Imm8(JitWriter *jit, jit_int8_t disp)

  1231 {

  1232 	jitoffs_t ptr;

  1233 	jit->write_ubyte(IA32_JMP_IMM8);

  1234 	ptr = jit->get_outputpos();

  1235 	jit->write_byte(disp);

  1236 	return ptr;

  1237 }

  1239 inline jitoffs_t IA32_Jump_Cond_Imm32(JitWriter *jit, jit_uint8_t cond, jit_int32_t disp)

  1240 {

  1241 	jitoffs_t ptr;

  1242 	jit->write_ubyte(IA32_JCC_IMM32_1);

  1243 	jit->write_ubyte(IA32_JCC_IMM32_2+cond);

  1244 	ptr = jit->get_outputpos();

  1245 	jit->write_int32(disp);

  1246 	return ptr;

  1247 }

  1249 inline void IA32_Jump_Reg(JitWriter *jit, jit_uint8_t reg)

  1250 {

  1251 	jit->write_ubyte(IA32_JMP_RM);

  1252 	jit->write_ubyte(ia32_modrm(MOD_REG, 4, reg));

  1253 }

  1255 inline void IA32_Jump_Rm(JitWriter *jit, jit_uint8_t reg, jit_uint8_t mode)

  1256 {

  1257 	jit->write_ubyte(IA32_JMP_RM);

  1258 	jit->write_ubyte(ia32_modrm(mode, 4, reg));

  1259 }

  1261 inline jitoffs_t IA32_Call_Imm32(JitWriter *jit, jit_int32_t disp)

  1262 {

  1263 	jitoffs_t ptr;

  1264 	jit->write_ubyte(IA32_CALL_IMM32);

  1265 	ptr = jit->get_outputpos();

  1266 	jit->write_int32(disp);

  1267 	return ptr;

  1268 }

  1270 inline void IA32_Call_Reg(JitWriter *jit, jit_uint8_t reg)

  1271 {

  1272 	jit->write_ubyte(IA32_CALL_RM);

  1273 	jit->write_ubyte(ia32_modrm(MOD_REG, 2, reg));

  1274 }

  1276 inline void IA32_Write_Jump8(JitWriter *jit, jitoffs_t jmp, jitoffs_t target)

  1277 {

  1278 	//save old ptr

  1279 	jitcode_t oldptr = jit->outptr;

  1280 	//get relative difference

  1281 	jit_int8_t diff = (target - (jmp + 1));

  1282 	//overwrite old value

  1283 	jit->outptr = jit->outbase + jmp;

  1284 	jit->write_byte(diff);

  1285 	//restore old ptr

  1286 	jit->outptr = oldptr;

  1287 }

  1289 inline void IA32_Write_Jump32(JitWriter *jit, jitoffs_t jmp, jitoffs_t target)

  1290 {

  1291 	//save old ptr

  1292 	jitcode_t oldptr = jit->outptr;

  1293 	//get relative difference

  1294 	jit_int32_t diff = (target - (jmp + 4));

  1295 	//overwrite old value

  1296 	jit->outptr = jit->outbase + jmp;

  1297 	jit->write_int32(diff);

  1298 	//restore old ptr

  1299 	jit->outptr = oldptr;

  1300 }

  1302 /**

  1303  * Corrects a jump using an absolute offset, not a relative one.

  1304  */

  1305 inline void IA32_Write_Jump32_Abs(JitWriter *jit, jitoffs_t jmp, void *target)

  1306 {

  1307 	//save old ptr

  1308 	jitcode_t oldptr = jit->outptr;

  1309 	//get relative difference

  1310 	long diff = ((long)target - ((long)jit->outbase + jmp + 4));

  1311 	//overwrite old value

  1312 	jit->outptr = jit->outbase + jmp;

  1313 	jit->write_int32(diff);

  1314 	//restore old ptr

  1315 	jit->outptr = oldptr;

  1316 }

  1318 /* For writing and auto-calculating an absolute target */

  1319 inline void IA32_Jump_Imm32_Abs(JitWriter *jit, jitoffs_t target)

  1320 {

  1321 	/* :TODO: this should work, but does it? */

  1322 	jit->write_ubyte(IA32_JMP_IMM32);

  1323 	IA32_Write_Jump32(jit, jit->get_outputpos(), target);

  1324 	jit->outptr += 4;

  1325 }

  1327 inline void IA32_Jump_Cond_Imm32_Abs(JitWriter *jit, jit_uint8_t cond, jitoffs_t target)

  1328 {

  1329 	/* :TODO: this should work, but does it? */

  1330 	jit->write_ubyte(IA32_JCC_IMM32_1);

  1331 	jit->write_ubyte(IA32_JCC_IMM32_2+cond);

  1332 	IA32_Write_Jump32(jit, jit->get_outputpos(), target);

  1333 	jit->outptr += 4;

  1334 }

  1336 inline void IA32_Send_Jump8_Here(JitWriter *jit, jitoffs_t jmp)

  1337 {

  1338 	jitoffs_t curptr = jit->get_outputpos();

  1339 	IA32_Write_Jump8(jit, jmp, curptr);

  1340 }

  1342 inline void IA32_Send_Jump32_Here(JitWriter *jit, jitoffs_t jmp)

  1343 {

  1344 	jitoffs_t curptr = jit->get_outputpos();

  1345 	IA32_Write_Jump32(jit, jmp, curptr);

  1346 }

  1348 inline void IA32_Return(JitWriter *jit)

  1349 {

  1350 	jit->write_ubyte(IA32_RET);

  1351 }

  1353 inline void IA32_Return_Popstack(JitWriter *jit, unsigned short bytes)

  1354 {

  1355 	jit->write_ubyte(IA32_RETN);

  1356 	jit->write_ushort(bytes);

  1357 }

  1359 inline void IA32_Test_Rm_Reg(JitWriter *jit, jit_uint8_t reg1, jit_uint8_t reg2, jit_uint8_t mode)

  1360 {

  1361 	jit->write_ubyte(IA32_TEST_RM_REG);

  1362 	jit->write_ubyte(ia32_modrm(mode, reg2, reg1));

  1363 }

  1365 inline void IA32_Cmp_Rm_Reg(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

  1366 {

  1367 	jit->write_ubyte(IA32_CMP_RM_REG);

  1368 	jit->write_ubyte(ia32_modrm(mode, src, dest));

  1369 }

  1371 inline void IA32_Cmp_Reg_Rm(JitWriter *jit, jit_uint8_t dest, jit_uint8_t src, jit_uint8_t mode)

  1372 {

  1373 	jit->write_ubyte(IA32_CMP_REG_RM);

  1374 	jit->write_ubyte(ia32_modrm(mode, dest, src));

  1375 }

  1377 inline void IA32_Cmp_Reg_Rm_ESP(JitWriter *jit, jit_uint8_t cmpreg)

  1378 {

  1379 	jit->write_ubyte(IA32_CMP_REG_RM);

  1380 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, cmpreg, REG_SIB));

  1381 	jit->write_ubyte(ia32_sib(NOSCALE, REG_NOIDX, REG_ESP));

  1382 }

  1384 inline void IA32_Cmp_Reg_Rm_Disp8(JitWriter *jit, jit_uint8_t reg1, jit_uint8_t reg2, jit_int8_t disp8)

  1385 {

  1386 	jit->write_ubyte(IA32_CMP_REG_RM);

  1387 	jit->write_ubyte(ia32_modrm(MOD_DISP8, reg1, reg2));

  1388 	jit->write_byte(disp8);

  1389 }

  1391 inline void IA32_Cmp_Rm_Imm8(JitWriter *jit, jit_uint8_t mode, jit_uint8_t rm, jit_int8_t imm8)

  1392 {

  1393 	jit->write_ubyte(IA32_CMP_RM_IMM8);

  1394 	jit->write_ubyte(ia32_modrm(mode, 7, rm));

  1395 	jit->write_byte(imm8);

  1396 }

  1398 inline void IA32_Cmp_Rm_Imm32(JitWriter *jit, jit_uint8_t mode, jit_uint8_t rm, jit_int32_t imm32)

  1399 {

  1400 	jit->write_ubyte(IA32_CMP_RM_IMM32);

  1401 	jit->write_ubyte(ia32_modrm(mode, 7, rm));

  1402 	jit->write_int32(imm32);

  1403 }

  1405 inline void IA32_Cmp_Rm_Imm32_Disp8(JitWriter *jit, jit_uint8_t reg, jit_int8_t disp8, jit_int32_t imm32)

  1406 {

  1407 	jit->write_ubyte(IA32_CMP_RM_IMM32);

  1408 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 7, reg));

  1409 	jit->write_byte(disp8);

  1410 	jit->write_int32(imm32);

  1411 }

  1413 inline void IA32_Cmp_Rm_Disp8_Imm8(JitWriter *jit, jit_uint8_t reg, jit_int8_t disp, jit_int8_t imm8)

  1414 {

  1415 	jit->write_ubyte(IA32_CMP_RM_IMM8);

  1416 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 7, reg));

  1417 	jit->write_byte(disp);

  1418 	jit->write_byte(imm8);

  1419 }

  1421 inline void IA32_Cmp_Al_Imm8(JitWriter *jit, jit_int8_t value)

  1422 {

  1423 	jit->write_ubyte(IA32_CMP_AL_IMM32);

  1424 	jit->write_byte(value);

  1425 }

  1427 inline void IA32_Cmp_Eax_Imm32(JitWriter *jit, jit_int32_t value)

  1428 {

  1429 	jit->write_ubyte(IA32_CMP_EAX_IMM32);

  1430 	jit->write_int32(value);

  1431 }

  1433 inline void IA32_SetCC_Rm8(JitWriter *jit, jit_uint8_t reg, jit_uint8_t cond)

  1434 {

  1435 	jit->write_ubyte(IA32_SETCC_RM8_1);

  1436 	jit->write_ubyte(IA32_SETCC_RM8_2+cond);

  1437 	jit->write_ubyte(ia32_modrm(MOD_REG, 0, reg));

  1438 }

  1440 inline void IA32_CmovCC_Rm(JitWriter *jit, jit_uint8_t src, jit_uint8_t cond)

  1441 {

  1442 	jit->write_ubyte(IA32_CMOVCC_RM_1);

  1443 	jit->write_ubyte(IA32_CMOVCC_RM_2+cond);

  1444 	jit->write_ubyte(ia32_modrm(MOD_MEM_REG, 0, src));

  1445 }

  1447 inline void IA32_CmovCC_Rm_Disp8(JitWriter *jit, jit_uint8_t src, jit_uint8_t cond, jit_int8_t disp)

  1448 {

  1449 	jit->write_ubyte(IA32_CMOVCC_RM_1);

  1450 	jit->write_ubyte(IA32_CMOVCC_RM_2+cond);

  1451 	jit->write_ubyte(ia32_modrm(MOD_DISP8, 0, src));

  1452 	jit->write_byte(disp);

  1453 }

  1455 inline void IA32_Cmpsb(JitWriter *jit)

  1456 {

  1457 	jit->write_ubyte(IA32_CMPSB);

  1458 }

  1460 inline void IA32_Rep(JitWriter *jit)

  1461 {

  1462 	jit->write_ubyte(IA32_REP);

  1463 }

  1465 inline void IA32_Movsd(JitWriter *jit)

  1466 {

  1467 	jit->write_ubyte(IA32_MOVSD);

  1468 }

  1470 inline void IA32_Movsb(JitWriter *jit)

  1471 {

  1472 	jit->write_ubyte(IA32_MOVSB);

  1473 }

  1475 inline void IA32_Stosd(JitWriter *jit)

  1476 {

  1477 	jit->write_ubyte(IA32_STOSD);

  1478 }

  1480 inline void IA32_Cld(JitWriter *jit)

  1481 {

  1482 	jit->write_ubyte(IA32_CLD);

  1483 }

  1485 #endif //_INCLUDE_JIT_X86_MACROS_H

author	Scott Ehlert <ds@alliedmods.net>
	Sun Jul 15 08:00:26 2007 +0000 (2007-07-15)
changeset 1116	40cc5e9f0f1b
parent 1009	06fd81fdedfb
child 1167	57211cde9ffc
permissions	-rw-r--r--