sourcemod-central: sourcepawn/vm/jit/x86/opcode

     1 #include <limits.h>

     2 #include <string.h>

     3 #include "jit_x86.h"

     4 #include "opcode_helpers.h"

     5 #include "x86_macros.h"

     7 int OpAdvTable[OP_NUM_OPCODES];

     9 jitoffs_t Write_Execute_Function(JitWriter *jit, bool never_inline)

    10 {

    11 	/**

    12 	 * The variables we're passed in:

    13 	 *  sp_context_t *ctx, uint32_t code_idx, cell_t *result

    14 	 */

    16 	/**

    17 	 * !NOTE!

    18 	 * Currently, we do not accept ctx->frm as the new frame pointer.

    19 	 * Instead, we copy the frame from the stack pointer.

    20 	 * This is because we do not support resuming or sleeping!

    21 	 */

    23 	//push ebp

    24 	//mov ebp, esp

    25 	IA32_Push_Reg(jit, REG_EBP);

    26 	IA32_Mov_Reg_Rm(jit, REG_EBP, REG_ESP, MOD_REG);

    28 	//push esi

    29 	//push edi

    30 	//push ebx

    31 	IA32_Push_Reg(jit, REG_ESI);

    32 	IA32_Push_Reg(jit, REG_EDI);

    33 	IA32_Push_Reg(jit, REG_EBX);

    35 	//sub esp, 4*6	- allocate info array

    36 	//mov esi, esp	- save info pointer

    37 	IA32_Sub_Rm_Imm8(jit, REG_ESP, 4*6, MOD_REG);

    38 	IA32_Mov_Reg_Rm(jit, AMX_REG_INFO, REG_ESP, MOD_REG);

    40 	/* Initial memory setup */

    41 	//mov eax, [ebp+16]		- get result pointer

    42 	//mov [esi+8], eax		- store into info pointer

    43 	//mov eax, [ebp+8]		- get context

    44 	//mov [esi+12], eax		- store context into info pointer

    45 	//mov ecx, [eax+<offs>]	- get heap pointer

    46 	//mov [esi+4], ecx		- store heap into info pointer

    47 	//mov edi, [eax+<offs>]	- get data pointer

    48 	IA32_Mov_Reg_Rm_Disp8(jit, REG_EAX, REG_EBP, 16);

    49 	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, REG_EAX, AMX_INFO_RETVAL);

    50 	IA32_Mov_Reg_Rm_Disp8(jit, REG_EAX, REG_EBP, 8);

    51 	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, REG_EAX, AMX_INFO_CONTEXT);

    52 	IA32_Mov_Reg_Rm_Disp8(jit, REG_ECX, REG_EAX, offsetof(sp_context_t, hp));

    53 	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, REG_ECX, AMX_INFO_HEAP);

    54 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_DAT, REG_EAX, offsetof(sp_context_t, data));

    56 	/* Frame setup */

    57 	//mov ebp, [eax+<offs>]	- get stack pointer

    58 	//add ebp, edi			- relocate to data section

    59 	//mov ebx, ebp			- copy sp to frm

    60 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_STK, REG_EAX, offsetof(sp_context_t, sp));

    61 	IA32_Add_Rm_Reg(jit, REG_EBP, AMX_REG_STK, AMX_REG_DAT);

    62 	IA32_Mov_Reg_Rm(jit, AMX_REG_FRM, AMX_REG_STK, MOD_REG);

    64 	/* Info memory setup */

    65 	//mov ecx, edi			- copy base of data to temp var

    66 	//add ecx, [eax+<offs>] - add memsize to get stack top

    67 	//mov [esi+16], ecx		- store stack top into info pointer

    68 	//mov ecx, [eax+<offs>] - get heap low

    69 	//mov [esi+20], ecx		- store heap low into info pointer

    70 	IA32_Mov_Reg_Rm(jit, REG_ECX, AMX_REG_DAT, MOD_REG);

    71 	IA32_Add_Reg_Rm_Disp8(jit, REG_ECX, REG_EAX, offsetof(sp_context_t, memory));

    72 	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, REG_ECX, AMX_INFO_STACKTOP);

    73 	IA32_Mov_Reg_Rm_Disp8(jit, REG_ECX, REG_EAX, offsetof(sp_context_t, heapbase));

    74 	IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_INFO, REG_ECX, AMX_INFO_HEAPLOW);

    76 	/* Remaining needed vars */

    77 	//mov ecx, [ebp+12]		- get code index

    78 	//add ecx, [eax+<offs>] - add code base to index

    79 	//mov edx, [eax+<offs>]	- get alt

    80 	//mov eax, [eax+<offs>] - get pri

    81 	IA32_Mov_Reg_Rm_Disp8(jit, REG_ECX, REG_EBP, 12);

    82 	IA32_Add_Reg_Rm_Disp8(jit, REG_ECX, REG_EAX, offsetof(sp_context_t, base));

    83 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_ALT, REG_EAX, offsetof(sp_context_t, alt));

    84 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_PRI, REG_EAX, offsetof(sp_context_t, pri));

    86 	/* by now, everything is set up, so we can call into the plugin */

    87 	//call ecx

    88 	IA32_Call_Reg(jit, REG_ECX);

    90 	/* if the code flow gets to here, there was a normal return */

    91 	//mov ebp, [esi+8]		- get retval pointer

    92 	//mov [ebp], eax		- store retval from PRI

    93 	//mov eax, SP_ERR_NONE	- set no error

    94 	IA32_Mov_Reg_Rm_Disp8(jit, REG_EBP, AMX_REG_INFO, AMX_INFO_RETVAL);

    95 	IA32_Mov_Rm_Reg(jit, REG_EBP, AMX_REG_PRI, MOD_MEM_REG);

    96 	IA32_Mov_Reg_Imm32(jit, REG_EAX, SP_ERR_NONE);

    98 	/* save where error checking/halting functions should go to */

    99 	jitoffs_t offs_return;

   100 	CompData *data = (CompData *)jit->data;

   101 	if (!(data->inline_level & JIT_INLINE_ERRORCHECKS))

   102 	{

   103 		/* We have to write code assume we're breaking out of a call */

   104 		//jmp [past the next instruction]

   105 		//add esp, 4

   106 		jitoffs_t offs = IA32_Jump_Imm8(jit, 0);

   107 		offs_return = jit->jit_curpos();

   108 		IA32_Sub_Rm_Imm8(jit, REG_ESP, 4, MOD_REG);

   109 		IA32_Send_Jump8_Here(jit, offs);

   110 	} else {

   111 		offs_return = jit->jit_curpos();

   112 	}

   114 	/* _FOR NOW_ ...

   115 	 * We are _not_ going to restore anything that was on the stack.

   116 	 * This is a tiny, useless optimization based on the fact that

   117 	 * BaseContext::Execute() automatically restores our values anyway.

   118 	 */

   120 	//add esp, 4*6

   121 	//pop ebx

   122 	//pop edi

   123 	//pop esi

   124 	//pop ebp

   125 	//ret

   126 	IA32_Add_Rm_Imm8(jit, REG_ESP, 4*6, MOD_REG);

   127 	IA32_Pop_Reg(jit, REG_EBX);

   128 	IA32_Pop_Reg(jit, REG_EDI);

   129 	IA32_Pop_Reg(jit, REG_ESI);

   130 	IA32_Pop_Reg(jit, REG_EBP);

   131 	IA32_Return(jit);

   133 	return offs_return;

   134 }

   136 void Write_BreakDebug(JitWriter *jit)

   137 {

   138 	//push ecx

   139 	//mov ecx, [esi+ctx]

   140 	//cmp [ecx+dbreak], 0

   141 	//jnz :nocall

   142 	IA32_Push_Reg(jit, AMX_REG_TMP);

   143 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_CONTEXT);

   144 	IA32_Cmp_Rm_Imm32_Disp8(jit, AMX_REG_TMP, offsetof(sp_context_t, dbreak), 0);

   145 	jitoffs_t jmp = IA32_Jump_Cond_Imm8(jit, CC_NZ, 0);

   147 	//pushad

   148 	IA32_Pushad(jit);

   150 	//push [esi+frm]

   151 	//push [ecx+context]

   152 	//mov ecx, [ecx+dbreak]

   153 	//call ecx

   154 	//add esp, 8

   155 	//popad

   156 	IA32_Push_Rm_Disp8(jit, AMX_REG_INFO, AMX_INFO_FRAME);

   157 	IA32_Push_Rm_Disp8(jit, AMX_REG_TMP, offsetof(sp_context_t, context));

   158 	IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_TMP, offsetof(sp_context_t, dbreak));

   159 	IA32_Call_Reg(jit, AMX_REG_TMP);

   160 	IA32_Add_Rm_Imm8(jit, REG_ESP, 4*2, MOD_REG);

   161 	IA32_Popad(jit);

   163 	//:nocall

   164 	IA32_Send_Jump8_Here(jit, jmp);

   165 	IA32_Add_Rm_Imm8(jit, REG_ESP, 4*1, MOD_REG);

   166 	IA32_Return(jit);

   167 }

   169 void Write_Error(JitWriter *jit, int error)

   170 {

   171 	CompData *data = (CompData *)jit->data;

   173 	/* These are so small that we always inline them! */

   174 	//mov eax, <error>

   175 	//jmp [...jit_return]

   176 	IA32_Mov_Reg_Imm32(jit, REG_EAX, error);

   177 	jitoffs_t jmp = IA32_Jump_Imm32(jit, 0);

   178 	IA32_Write_Jump32(jit, jmp, data->jit_return);

   179 }

   181 void Write_Check_DivZero(JitWriter *jit, jit_uint8_t reg)

   182 {

   183 	CompData *data = (CompData *)jit->data;

   185 	//test reg, reg

   186 	//jnz :continue

   187 	//divzero: (write error)

   188 	IA32_Test_Rm_Reg(jit, reg, reg, MOD_REG);

   189 	jitoffs_t jmp = IA32_Jump_Cond_Imm8(jit, CC_NZ, 0);

   190 	if (!(data->inline_level & JIT_INLINE_ERRORCHECKS))

   191 	{

   192 		//sub esp, 4    - correct stack for returning to non-inlined JIT

   193 		IA32_Sub_Rm_Imm8(jit, REG_ESP, 4, MOD_REG);

   194 	}

   195 	Write_Error(jit, SP_ERR_DIVIDE_BY_ZERO);

   196 	//continue:

   197 	IA32_Send_Jump8_Here(jit, jmp);

   199 }

   201 void Write_Check_VerifyAddr(JitWriter *jit, jit_uint8_t reg, bool firstcall)

   202 {

   203 	CompData *data = (CompData *)jit->data;

   205 	/* :TODO: Should this be checking for below heaplow?

   206 	 * The old JIT did not.

   207 	 */

   209 	if (!data->checks)

   210 	{

   211 		return;

   212 	}

   214 	bool call = false;

   215 	if (!(data->inline_level & JIT_INLINE_ERRORCHECKS))

   216 	{

   217 		/* If we're not in the initial generation phase,

   218 		 * Write a call to the actual routine instead.

   219 		 */

   220 		if (!firstcall)

   221 		{

   222 			jitoffs_t call = IA32_Call_Imm32(jit, 0);

   223 			if (reg == REG_EAX)

   224 			{

   225 				IA32_Write_Jump32(jit, call, data->jit_verify_addr_eax);

   226 			} else if (reg == REG_EDX) {

   227 				IA32_Write_Jump32(jit, call, data->jit_verify_addr_edx);

   228 			}

   229 			return;

   230 		}

   231 		call = true;

   232 	} else if (firstcall) {

   233 		/* Inline + initial gen == no code */

   234 		return;

   235 	}

   237 	//cmp reg, [stp]

   238 	//jae memaccess

   239 	//cmp reg, [hea]

   240 	//jb continue

   241 	//lea ecx, [reg+edi]

   242 	//cmp ecx, ebp

   243 	//jae continue

   244 	//memaccess: (write error)

   245 	//continue:

   246 	IA32_Cmp_Reg_Rm_Disp8(jit, reg, AMX_REG_INFO, AMX_INFO_STACKTOP);

   247 	jitoffs_t jmp1 = IA32_Jump_Cond_Imm8(jit, CC_AE, 0);

   248 	IA32_Cmp_Reg_Rm_Disp8(jit, reg, AMX_REG_INFO, AMX_INFO_HEAP);

   249 	jitoffs_t jmp2 = IA32_Jump_Cond_Imm8(jit, CC_B, 0);

   250 	IA32_Lea_Reg_DispRegMult(jit, AMX_REG_TMP, reg, AMX_REG_DAT, NOSCALE);

   251 	IA32_Cmp_Rm_Reg(jit, AMX_REG_TMP, AMX_REG_STK, MOD_REG);

   252 	jitoffs_t jmp3 = IA32_Jump_Cond_Imm8(jit, CC_AE, 0);

   253 	IA32_Send_Jump8_Here(jit, jmp1);

   254 	Write_Error(jit, SP_ERR_MEMACCESS);

   255 	IA32_Send_Jump8_Here(jit, jmp2);

   256 	IA32_Send_Jump8_Here(jit, jmp3);

   257 	if (call)

   258 	{

   259 		IA32_Return(jit);

   260 	}

   261 }

   263 void Write_BoundsCheck(JitWriter *jit)

   264 {

   265 	CompData *data = (CompData *)jit->data;

   266 	bool always_inline = ((data->inline_level & JIT_INLINE_ERRORCHECKS) == JIT_INLINE_ERRORCHECKS);

   268 	/* :TODO: break out on high -O level? */

   270 	if (!always_inline)

   271 	{

   272 		if (data->jit_bounds)

   273 		{

   274 			/* just generate the call */

   275 			//mov ecx, <val>

   276 			//call <offs>

   277 			IA32_Mov_Reg_Imm32(jit, AMX_REG_TMP, jit->read_cell());

   278 			jitoffs_t call = IA32_Call_Imm32(jit, 0);

   279 			IA32_Write_Jump32(jit, call, data->jit_bounds);

   280 		} else {

   281 			//cmp eax, 0

   282 			//jl :err_bounds

   283 			//cmp eax, ecx

   284 			//jg :err_bounds

   285 			//ret

   286 			IA32_Cmp_Rm_Imm32(jit, MOD_REG, AMX_REG_PRI, 0);

   287 			jitoffs_t jmp1 = IA32_Jump_Cond_Imm8(jit, CC_L, 0);

   288 			//:TODO: make sure this is right order

   289 			IA32_Cmp_Rm_Reg(jit, AMX_REG_PRI, AMX_REG_TMP, MOD_REG);

   290 			jitoffs_t jmp2 = IA32_Jump_Cond_Imm8(jit, CC_G, 0);

   291 			IA32_Return(jit);

   292 			IA32_Send_Jump8_Here(jit, jmp1);

   293 			IA32_Send_Jump8_Here(jit, jmp2);

   294 			Write_Error(jit, SP_ERR_ARRAY_BOUNDS);

   295 		}

   296 	} else {

   297 		//cmp eax, 0

   298 		//jl :err_bounds

   299 		IA32_Cmp_Rm_Imm32(jit, MOD_REG, AMX_REG_PRI, 0);

   300 		jitoffs_t jmp1 = IA32_Jump_Cond_Imm8(jit, CC_L, 0);

   301 		//cmp eax, <val>

   302 		//jg :err_bounds

   303 		IA32_Cmp_Rm_Imm32(jit, MOD_REG, AMX_REG_PRI, jit->read_cell());

   304 		jitoffs_t jmp2 = IA32_Jump_Cond_Imm8(jit, CC_G, 0);

   305 		//jmp :continue

   306 		jitoffs_t cont = IA32_Jump_Imm8(jit, 0);

   307 		//:err_bounds

   308 		IA32_Send_Jump8_Here(jit, jmp1);

   309 		IA32_Send_Jump8_Here(jit, jmp2);

   310 		Write_Error(jit, SP_ERR_ARRAY_BOUNDS);

   311 		//:continue

   312 		IA32_Send_Jump8_Here(jit, cont);

   313 	}

   314 }

   316 void Write_CheckMargin_Heap(JitWriter *jit)

   317 {

   318 	CompData *data = (CompData *)jit->data;

   320 	bool always_inline = ((data->inline_level & JIT_INLINE_ERRORCHECKS) == JIT_INLINE_ERRORCHECKS);

   322 	if (!always_inline && data->jit_chkmargin_heap)

   323 	{

   324 		/* just generate the call */

   325 		jitoffs_t call = IA32_Call_Imm32(jit, 0);

   326 		IA32_Write_Jump32(jit, call, data->jit_chkmargin_heap);

   327 	} else {

   328 		//mov ecx, [esi+hea]

   329 		//cmp ecx, [esi+hlw]

   330 		//jl :error_heapmin

   331 		IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAP);

   332 		IA32_Cmp_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_INFO, AMX_INFO_HEAPLOW);

   333 		jitoffs_t hm = IA32_Jump_Cond_Imm8(jit, CC_L, 0);

   334 		//lea ecx, [edi+ecx+STACK_MARGIN]

   335 		//cmp ecx, ebp

   336 		// jg :error_heaplow

   337 		//OR

   338 		// ret

   339 		IA32_Lea_Reg_DispRegMultImm8(jit, AMX_REG_TMP, AMX_REG_DAT, AMX_REG_TMP, NOSCALE, STACK_MARGIN);

   340 		IA32_Cmp_Rm_Reg(jit, REG_ECX, AMX_REG_STK, MOD_REG);

   341 		jitoffs_t hl = IA32_Jump_Cond_Imm8(jit, CC_G, 0);

   342 		jitoffs_t cont;

   343 		if (always_inline)

   344 		{

   345 			cont = IA32_Jump_Imm8(jit, 0);

   346 		} else {

   347 			IA32_Return(jit);

   348 		}

   349 		//:error_heapmin

   350 		IA32_Send_Jump8_Here(jit, hm);

   351 		Write_Error(jit, SP_ERR_HEAPMIN);

   352 		//:error_heaplow

   353 		IA32_Send_Jump8_Here(jit, hl);

   354 		Write_Error(jit, SP_ERR_HEAPLOW);

   355 		//:continue

   356 		if (!always_inline)

   357 		{

   358 			IA32_Send_Jump8_Here(jit, cont);

   359 		}

   360 	}

   361 }

   363 void Write_CheckMargin_Stack(JitWriter *jit)

   364 {

   365 	/* this is small, so we always inline it.

   366 	*/

   367 	//cmp ebp, [esi+stp]

   368 	//jle :continue

   369 	IA32_Cmp_Reg_Rm_Disp8(jit, AMX_REG_STK, AMX_REG_INFO, AMX_INFO_STACKTOP);

   370 	jitoffs_t jmp = IA32_Jump_Cond_Imm8(jit, CC_LE, 0);

   371 	if (!(((CompData *)jit->data)->inline_level & JIT_INLINE_ERRORCHECKS))

   372 	{

   373 		//sub esp, 4	- correct stack for returning to non-inlined JIT

   374 		IA32_Sub_Rm_Imm8(jit, REG_ESP, 4, MOD_REG);

   375 	}

   376 	Write_Error(jit, SP_ERR_STACKMIN);

   377 	//continue:

   378 	IA32_Send_Jump8_Here(jit, jmp);

   379 }

   381 void Macro_PushN_Addr(JitWriter *jit, int i)

   382 {

   383 	//push eax

   384 	//mov eax, frm

   385 	//loop i times:

   386 	// lea ecx, [eax+<val>]

   387 	// mov [ebp-4*i], ecx

   388 	//sub ebp, 4*N

   389 	//pop eax

   391 	cell_t val;

   392 	int n = 1;

   393 	IA32_Push_Reg(jit, AMX_REG_PRI);

   394 	IA32_Mov_Reg_Rm(jit, AMX_REG_PRI, AMX_INFO_FRM, MOD_MEM_REG);

   395 	do

   396 	{

   397 		val = jit->read_cell();

   398 		if (val < SCHAR_MAX && val > SCHAR_MIN)

   399 			IA32_Lea_DispRegImm8(jit, AMX_REG_TMP, AMX_REG_PRI, (jit_int8_t)val);

   400 		else

   401 			IA32_Lea_DispRegImm32(jit, AMX_REG_TMP, AMX_REG_PRI, val);

   402 		IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_TMP, -4*n);

   403 	} while (n++ < i);

   404 	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4*i, MOD_REG);

   405 	IA32_Pop_Reg(jit, AMX_REG_PRI);

   406 }

   408 void Macro_PushN_S(JitWriter *jit, int i)

   409 {

   410 	//loop i times:

   411 	// mov ecx, [ebx+<val>]

   412 	// mov [ebp-4*i], ecx

   413 	//sub ebp, 4*N

   415 	cell_t val;

   416 	int n = 1;

   417 	do

   418 	{

   419 		val = jit->read_cell();

   420 		if (val < SCHAR_MAX && val > SCHAR_MIN)

   421 			IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_FRM, (jit_int8_t)val);

   422 		else

   423 			IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_FRM, val);

   424 		IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_TMP, -4*n);

   425 	} while (n++ < i);

   426 	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4*i, MOD_REG);

   427 }

   429 void Macro_PushN_C(JitWriter *jit, int i)

   430 {

   431 	//loop i times:

   432 	// mov [ebp-4*i], <val>

   433 	//sub ebp, 4*N

   435 	int n = 1;

   436 	do

   437 	{

   438 		IA32_Mov_Rm_Imm32_Disp8(jit, AMX_REG_STK, jit->read_cell(), -4*n);

   439 	} while (n++ < i);

   440 	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4*i, MOD_REG);

   441 }

   443 void Macro_PushN(JitWriter *jit, int i)

   444 {

   445 	//loop i times:

   446 	// mov ecx, [edi+<val>]

   447 	// mov [ebp-4*i], ecx

   448 	//sub ebp, 4*N

   450 	cell_t val;

   451 	int n = 1;

   452 	do

   453 	{

   454 		val = jit->read_cell();

   455 		if (val < SCHAR_MAX && val > SCHAR_MIN)

   456 			IA32_Mov_Reg_Rm_Disp8(jit, AMX_REG_TMP, AMX_REG_DAT, (jit_int8_t)val);

   457 		else

   458 			IA32_Mov_Reg_Rm_Disp32(jit, AMX_REG_TMP, AMX_REG_DAT, val);

   459 		IA32_Mov_Rm_Reg_Disp8(jit, AMX_REG_STK, AMX_REG_TMP, -4*n);

   460 	} while (n++ < i);

   461 	IA32_Sub_Rm_Imm8(jit, AMX_REG_STK, 4*i, MOD_REG);

   462 }

   464 JITX86::JITX86()

   465 {

   466 	memset(OpAdvTable, -1, sizeof(OpAdvTable));

   468 	/* instructions with 5 parameters */

   469 	OpAdvTable[OP_PUSH5_C] = sizeof(cell_t)*5;

   470 	OpAdvTable[OP_PUSH5] = sizeof(cell_t)*5;

   471 	OpAdvTable[OP_PUSH5_S] = sizeof(cell_t)*5;

   472 	OpAdvTable[OP_PUSH5_ADR] = sizeof(cell_t)*5;

   474 	/* instructions with 4 parameters */

   475 	OpAdvTable[OP_PUSH4_C] = sizeof(cell_t)*4;

   476 	OpAdvTable[OP_PUSH4] = sizeof(cell_t)*4;

   477 	OpAdvTable[OP_PUSH4_S] = sizeof(cell_t)*4;

   478 	OpAdvTable[OP_PUSH4_ADR] = sizeof(cell_t)*4;

   480 	/* instructions with 3 parameters */

   481 	OpAdvTable[OP_PUSH3_C] = sizeof(cell_t)*3;

   482 	OpAdvTable[OP_PUSH3] = sizeof(cell_t)*3;

   483 	OpAdvTable[OP_PUSH3_S] = sizeof(cell_t)*3;

   484 	OpAdvTable[OP_PUSH3_ADR] = sizeof(cell_t)*3;

   486 	/* instructions with 2 parameters */

   487 	OpAdvTable[OP_PUSH2_C] = sizeof(cell_t)*2;

   488 	OpAdvTable[OP_PUSH2] = sizeof(cell_t)*2;

   489 	OpAdvTable[OP_PUSH2_S] = sizeof(cell_t)*2;

   490 	OpAdvTable[OP_PUSH2_ADR] = sizeof(cell_t)*2;

   491 	OpAdvTable[OP_LOAD_BOTH] = sizeof(cell_t)*2;

   492 	OpAdvTable[OP_LOAD_S_BOTH] = sizeof(cell_t)*2;

   493 	OpAdvTable[OP_CONST] = sizeof(cell_t)*2;

   494 	OpAdvTable[OP_CONST_S] = sizeof(cell_t)*2;

   495 	OpAdvTable[OP_SYSREQ_N] = sizeof(cell_t)*2;

   497 	/* instructions with 1 parameter */

   498 	OpAdvTable[OP_LOAD_PRI] = sizeof(cell_t);

   499 	OpAdvTable[OP_LOAD_ALT] = sizeof(cell_t);

   500 	OpAdvTable[OP_LOAD_S_PRI] = sizeof(cell_t);

   501 	OpAdvTable[OP_LOAD_S_ALT] = sizeof(cell_t);

   502 	OpAdvTable[OP_LREF_PRI] = sizeof(cell_t);

   503 	OpAdvTable[OP_LREF_ALT] = sizeof(cell_t);

   504 	OpAdvTable[OP_LREF_S_PRI] = sizeof(cell_t);

   505 	OpAdvTable[OP_LREF_S_ALT] = sizeof(cell_t);

   506 	OpAdvTable[OP_LODB_I] = sizeof(cell_t);

   507 	OpAdvTable[OP_CONST_PRI] = sizeof(cell_t);

   508 	OpAdvTable[OP_CONST_ALT] = sizeof(cell_t);

   509 	OpAdvTable[OP_ADDR_PRI] = sizeof(cell_t);

   510 	OpAdvTable[OP_ADDR_ALT] = sizeof(cell_t);

   511 	OpAdvTable[OP_STOR_PRI] = sizeof(cell_t);

   512 	OpAdvTable[OP_STOR_ALT] = sizeof(cell_t);

   513 	OpAdvTable[OP_STOR_S_PRI] = sizeof(cell_t);

   514 	OpAdvTable[OP_STOR_S_ALT] = sizeof(cell_t);

   515 	OpAdvTable[OP_SREF_PRI] = sizeof(cell_t);

   516 	OpAdvTable[OP_SREF_ALT] = sizeof(cell_t);

   517 	OpAdvTable[OP_SREF_S_PRI] = sizeof(cell_t);

   518 	OpAdvTable[OP_SREF_S_ALT] = sizeof(cell_t);

   519 	OpAdvTable[OP_STRB_I] = sizeof(cell_t);

   520 	OpAdvTable[OP_LIDX_B] = sizeof(cell_t);

   521 	OpAdvTable[OP_IDXADDR_B] = sizeof(cell_t);

   522 	OpAdvTable[OP_ALIGN_PRI] = sizeof(cell_t);

   523 	OpAdvTable[OP_ALIGN_ALT] = sizeof(cell_t);

   524 	OpAdvTable[OP_LCTRL] = sizeof(cell_t);

   525 	OpAdvTable[OP_SCTRL] = sizeof(cell_t);

   526 	OpAdvTable[OP_PUSH_C] = sizeof(cell_t);

   527 	OpAdvTable[OP_PUSH] = sizeof(cell_t);

   528 	OpAdvTable[OP_PUSH_S] = sizeof(cell_t);

   529 	OpAdvTable[OP_STACK] = sizeof(cell_t);

   530 	OpAdvTable[OP_HEAP] = sizeof(cell_t);

   531 	OpAdvTable[OP_JREL] = sizeof(cell_t);

   532 	OpAdvTable[OP_SHL_C_PRI] = sizeof(cell_t);

   533 	OpAdvTable[OP_SHL_C_ALT] = sizeof(cell_t);

   534 	OpAdvTable[OP_SHR_C_PRI] = sizeof(cell_t);

   535 	OpAdvTable[OP_SHR_C_ALT] = sizeof(cell_t);

   536 	OpAdvTable[OP_ADD_C] = sizeof(cell_t);

   537 	OpAdvTable[OP_SMUL_C] = sizeof(cell_t);

   538 	OpAdvTable[OP_ZERO] = sizeof(cell_t);

   539 	OpAdvTable[OP_ZERO_S] = sizeof(cell_t);

   540 	OpAdvTable[OP_EQ_C_PRI] = sizeof(cell_t);

   541 	OpAdvTable[OP_EQ_C_ALT] = sizeof(cell_t);

   542 	OpAdvTable[OP_INC] = sizeof(cell_t);

   543 	OpAdvTable[OP_INC_S] = sizeof(cell_t);

   544 	OpAdvTable[OP_DEC] = sizeof(cell_t);

   545 	OpAdvTable[OP_DEC_S] = sizeof(cell_t);

   546 	OpAdvTable[OP_MOVS] = sizeof(cell_t);

   547 	OpAdvTable[OP_CMPS] = sizeof(cell_t);

   548 	OpAdvTable[OP_FILL] = sizeof(cell_t);

   549 	OpAdvTable[OP_HALT] = sizeof(cell_t);

   550 	OpAdvTable[OP_BOUNDS] = sizeof(cell_t);

   551 	OpAdvTable[OP_PUSH_ADR] = sizeof(cell_t);

   552 	OpAdvTable[OP_PUSH_HEAP_C] = sizeof(cell_t);

   553 	OpAdvTable[OP_SYSREQ_C] = sizeof(cell_t);

   555 	/* instructions with 0 parameters */

   556 	OpAdvTable[OP_LOAD_I] = 0;

   557 	OpAdvTable[OP_STOR_I] = 0;

   558 	OpAdvTable[OP_LIDX] = 0;

   559 	OpAdvTable[OP_IDXADDR] = 0;

   560 	OpAdvTable[OP_MOVE_PRI] = 0;

   561 	OpAdvTable[OP_MOVE_ALT] = 0;

   562 	OpAdvTable[OP_XCHG] = 0;

   563 	OpAdvTable[OP_PUSH_PRI] = 0;

   564 	OpAdvTable[OP_PUSH_ALT] = 0;

   565 	OpAdvTable[OP_POP_PRI] = 0;

   566 	OpAdvTable[OP_POP_ALT] = 0;

   567 	OpAdvTable[OP_PROC] = 0;

   568 	OpAdvTable[OP_RET] = 0;

   569 	OpAdvTable[OP_RETN] = 0;

   570 	OpAdvTable[OP_CALL_PRI] = 0;

   571 	OpAdvTable[OP_SHL] = 0;

   572 	OpAdvTable[OP_SHR] = 0;

   573 	OpAdvTable[OP_SSHR] = 0;

   574 	OpAdvTable[OP_SMUL] = 0;

   575 	OpAdvTable[OP_SDIV] = 0;

   576 	OpAdvTable[OP_SDIV_ALT] = 0;

   577 	OpAdvTable[OP_UMUL] = 0;

   578 	OpAdvTable[OP_UDIV] = 0;

   579 	OpAdvTable[OP_UDIV_ALT] = 0;

   580 	OpAdvTable[OP_ADD] = 0;

   581 	OpAdvTable[OP_SUB] = 0;

   582 	OpAdvTable[OP_SUB_ALT] = 0;

   583 	OpAdvTable[OP_AND] = 0;

   584 	OpAdvTable[OP_OR] = 0;

   585 	OpAdvTable[OP_XOR] = 0;

   586 	OpAdvTable[OP_NOT] = 0;

   587 	OpAdvTable[OP_NEG] = 0;

   588 	OpAdvTable[OP_INVERT] = 0;

   589 	OpAdvTable[OP_ZERO_PRI] = 0;

   590 	OpAdvTable[OP_ZERO_ALT] = 0;

   591 	OpAdvTable[OP_SIGN_PRI] = 0;

   592 	OpAdvTable[OP_SIGN_ALT] = 0;

   593 	OpAdvTable[OP_EQ] = 0;

   594 	OpAdvTable[OP_NEQ] = 0;

   595 	OpAdvTable[OP_LESS] = 0;

   596 	OpAdvTable[OP_LEQ] = 0;

   597 	OpAdvTable[OP_GRTR] = 0;

   598 	OpAdvTable[OP_GEQ] = 0;

   599 	OpAdvTable[OP_SLESS] = 0;

   600 	OpAdvTable[OP_SLEQ] = 0;

   601 	OpAdvTable[OP_SGRTR] = 0;

   602 	OpAdvTable[OP_SGEQ] = 0;

   603 	OpAdvTable[OP_INC_PRI] = 0;

   604 	OpAdvTable[OP_INC_ALT] = 0;

   605 	OpAdvTable[OP_INC_I] = 0;

   606 	OpAdvTable[OP_DEC_PRI] = 0;

   607 	OpAdvTable[OP_DEC_ALT] = 0;

   608 	OpAdvTable[OP_DEC_I] = 0;

   609 	OpAdvTable[OP_JUMP_PRI] = 0;

   610 	OpAdvTable[OP_SWAP_PRI] = 0;

   611 	OpAdvTable[OP_SWAP_ALT] = 0;

   612 	OpAdvTable[OP_NOP] = 0;

   613 	OpAdvTable[OP_BREAK] = 0;

   614 	OpAdvTable[OP_HEAP_PRI] = 0;

   615 	OpAdvTable[OP_POP_HEAP_PRI] = 0;

   616 	OpAdvTable[OP_SYSREQ_PRI] = 0;

   618 	/* opcodes that need relocation */

   619 	OpAdvTable[OP_CALL] = -2;

   620 	OpAdvTable[OP_JUMP] = -2;

   621 	OpAdvTable[OP_JZER] = -2;

   622 	OpAdvTable[OP_JNZ] = -2;

   623 	OpAdvTable[OP_JEQ] = -2;

   624 	OpAdvTable[OP_JNEQ] = -2;

   625 	OpAdvTable[OP_JLESS] = -2;

   626 	OpAdvTable[OP_JLEQ] = -2;

   627 	OpAdvTable[OP_JGRTR] = -2;

   628 	OpAdvTable[OP_JGEQ] = -2;

   629 	OpAdvTable[OP_JSLESS] = -2;

   630 	OpAdvTable[OP_JSLEQ] = -2;

   631 	OpAdvTable[OP_JSGRTR] = -2;

   632 	OpAdvTable[OP_JSGEQ] = -2;

   633 	OpAdvTable[OP_SWITCH] = -2;

   635 	/* opcodes that are totally invalid */

   636 	OpAdvTable[OP_FILE] = -3;

   637 	OpAdvTable[OP_SYMBOL] = -3;

   638 	OpAdvTable[OP_LINE] = -3;

   639 	OpAdvTable[OP_SRANGE] = -3;

   640 	OpAdvTable[OP_SYMTAG] = -3;

   641 	OpAdvTable[OP_SYSREQ_D] = -3;

   642 	OpAdvTable[OP_SYSREQ_ND] = -3;

   643 	OpAdvTable[OP_PUSH_R] = -3;

   644 }

author	Borja Ferrer <faluco@alliedmods.net>
	Fri Sep 22 11:52:19 2006 +0000 (2006-09-22)
changeset 87	06e62d38fb55
parent 86	c7e9bbc9ab44
child 90	053ec3f1e8c9
permissions	-rw-r--r--